Blame - configs/chromebook_jerry_defconfig - filogic/uboot

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Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	1	CONFIG_ARM=y
				2	CONFIG_ARCH_ROCKCHIP=y
				3	CONFIG_SYS_MALLOC_F_LEN=0x2000
				4	CONFIG_ROCKCHIP_RK3288=y
				5	CONFIG_TARGET_CHROMEBOOK_JERRY=y
Simon Glass	94906e4	2016-01-21 19:45:17 -0700	[diff] [blame]	6	CONFIG_ROCKCHIP_FAST_SPL=y
Thomas Chou	3a077cd	2015-11-11 21:39:33 +0800	[diff] [blame]	7	CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glass	cf88b7c	2016-01-21 19:44:13 -0700	[diff] [blame]	8	CONFIG_DM_KEYBOARD=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	9	CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
				10	CONFIG_SPL_STACK_R=y
Simon Glass	3b4057b	2016-01-21 19:43:35 -0700	[diff] [blame]	11	CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rini	f852e73	2016-04-21 21:37:19 -0400	[diff] [blame]	12	CONFIG_HUSH_PARSER=y
Tom Rini	1d9ac83	2016-04-24 17:29:26 -0400	[diff] [blame]	13	CONFIG_CMD_BOOTZ=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	14	# CONFIG_CMD_IMLS is not set
Tom Rini	1d9ac83	2016-04-24 17:29:26 -0400	[diff] [blame]	15	CONFIG_CMD_MMC=y
Tom Rini	0f2dcb9	2016-04-22 16:41:25 -0400	[diff] [blame]	16	CONFIG_CMD_SF=y
				17	CONFIG_CMD_SPI=y
				18	CONFIG_CMD_I2C=y
				19	CONFIG_CMD_GPIO=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	20	# CONFIG_CMD_SETEXPR is not set
Tom Rini	0f2dcb9	2016-04-22 16:41:25 -0400	[diff] [blame]	21	CONFIG_CMD_DHCP=y
Tom Rini	1d9ac83	2016-04-24 17:29:26 -0400	[diff] [blame]	22	CONFIG_CMD_MII=y
Tom Rini	0f2dcb9	2016-04-22 16:41:25 -0400	[diff] [blame]	23	CONFIG_CMD_PING=y
Tom Rini	1d9ac83	2016-04-24 17:29:26 -0400	[diff] [blame]	24	CONFIG_CMD_CACHE=y
Tom Rini	0f2dcb9	2016-04-22 16:41:25 -0400	[diff] [blame]	25	CONFIG_CMD_TIME=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	26	CONFIG_CMD_PMIC=y
				27	CONFIG_CMD_REGULATOR=y
Tom Rini	1d9ac83	2016-04-24 17:29:26 -0400	[diff] [blame]	28	CONFIG_CMD_EXT2=y
				29	CONFIG_CMD_EXT4=y
				30	CONFIG_CMD_FAT=y
				31	CONFIG_CMD_FS_GENERIC=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	32	CONFIG_SPL_OF_CONTROL=y
Simon Glass	8d32f4b	2016-01-21 19:43:38 -0700	[diff] [blame]	33	CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	34	CONFIG_REGMAP=y
huang lin	dd8515e	2015-11-17 14:20:13 +0800	[diff] [blame]	35	CONFIG_SPL_REGMAP=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	36	CONFIG_SYSCON=y
Simon Glass	3b4057b	2016-01-21 19:43:35 -0700	[diff] [blame]	37	CONFIG_SPL_SYSCON=y
Simon Glass	70bad91	2016-01-21 19:43:49 -0700	[diff] [blame]	38	# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng	63c1098	2015-09-28 05:14:15 -0700	[diff] [blame]	39	CONFIG_CLK=y
				40	CONFIG_SPL_CLK=y
				41	CONFIG_ROCKCHIP_GPIO=y
Simon Glass	cf88b7c	2016-01-21 19:44:13 -0700	[diff] [blame]	42	CONFIG_I2C_CROS_EC_TUNNEL=y
Bin Meng	63c1098	2015-09-28 05:14:15 -0700	[diff] [blame]	43	CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glass	cf88b7c	2016-01-21 19:44:13 -0700	[diff] [blame]	44	CONFIG_I2C_MUX=y
				45	CONFIG_CROS_EC_KEYB=y
				46	CONFIG_CMD_CROS_EC=y
				47	CONFIG_CROS_EC=y
				48	CONFIG_CROS_EC_SPI=y
Simon Glass	af0b744	2016-01-21 19:43:36 -0700	[diff] [blame]	49	CONFIG_PWRSEQ=y
Stephen Warren	859f256	2016-05-12 12:03:35 -0600	[diff] [blame]	50	CONFIG_SYSRESET=y
Bin Meng	63c1098	2015-09-28 05:14:15 -0700	[diff] [blame]	51	CONFIG_DM_MMC=y
				52	CONFIG_ROCKCHIP_DWMMC=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	53	CONFIG_PINCTRL=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	54	CONFIG_SPL_PINCTRL=y
Simon Glass	2ac4648	2015-12-29 05:22:45 -0700	[diff] [blame]	55	# CONFIG_SPL_PINCTRL_FULL is not set
Heiko Stübner	66bd8d3	2016-07-16 00:17:13 +0200	[diff] [blame]	56	CONFIG_ROCKCHIP_RK3288_PINCTRL=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	57	CONFIG_DM_PMIC=y
Simon Glass	cf88b7c	2016-01-21 19:44:13 -0700	[diff] [blame]	58	# CONFIG_SPL_PMIC_CHILDREN is not set
Simon Glass	99ac701	2016-01-21 19:43:48 -0700	[diff] [blame]	59	CONFIG_PMIC_RK808=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	60	CONFIG_DM_REGULATOR=y
Simon Glass	abd2c15	2016-01-21 19:45:19 -0700	[diff] [blame]	61	CONFIG_DM_REGULATOR_FIXED=y
Simon Glass	99ac701	2016-01-21 19:43:48 -0700	[diff] [blame]	62	CONFIG_REGULATOR_RK808=y
Simon Glass	abd2c15	2016-01-21 19:45:19 -0700	[diff] [blame]	63	CONFIG_DM_PWM=y
				64	CONFIG_PWM_ROCKCHIP=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	65	CONFIG_RAM=y
				66	CONFIG_SPL_RAM=y
Bin Meng	63c1098	2015-09-28 05:14:15 -0700	[diff] [blame]	67	CONFIG_DEBUG_UART=y
				68	CONFIG_DEBUG_UART_BASE=0xff690000
				69	CONFIG_DEBUG_UART_CLOCK=24000000
				70	CONFIG_DEBUG_UART_SHIFT=2
Thomas Chou	a6cec01	2015-11-19 21:48:14 +0800	[diff] [blame]	71	CONFIG_SYS_NS16550=y
Simon Glass	3b4057b	2016-01-21 19:43:35 -0700	[diff] [blame]	72	CONFIG_ROCKCHIP_SPI=y
Simon Glass	abd2c15	2016-01-21 19:45:19 -0700	[diff] [blame]	73	CONFIG_DM_VIDEO=y
Anatolij Gustschin	4601eb4	2016-01-25 17:17:22 +0100	[diff] [blame]	74	CONFIG_DISPLAY=y
Simon Glass	abd2c15	2016-01-21 19:45:19 -0700	[diff] [blame]	75	CONFIG_VIDEO_ROCKCHIP=y
Tom Rini	b937b2e	2016-06-13 09:45:14 -0400	[diff] [blame]	76	CONFIG_USE_PRIVATE_LIBGCC=y
Simon Glass	2ac4648	2015-12-29 05:22:45 -0700	[diff] [blame]	77	CONFIG_USE_TINY_PRINTF=y
Simon Glass	9d5d1cc	2015-08-30 16:55:42 -0600	[diff] [blame]	78	CONFIG_CMD_DHRYSTONE=y
				79	CONFIG_ERRNO_STR=y