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Matt Porter884ea7b2015-05-05 15:00:24 -04001/*
2 * (C) Copyright 2011
3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
4 *
5 * (C) Copyright 2015
6 * Kamil Lulko, <rev13@wp.pl>
7 *
8 * Copyright 2015 ATS Advanced Telematics Systems GmbH
9 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#ifndef _MACH_STM32_H_
15#define _MACH_STM32_H_
16
17/*
18 * Peripheral memory map
19 */
20#define STM32_PERIPH_BASE 0x40000000
21#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
22#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
23#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00018000)
24
25#define STM32_BUS_MASK 0xFFFF0000
26
27/*
28 * Register maps
29 */
30struct stm32_des_regs {
31 u16 flash_size;
32 u16 pad1;
33 u32 pad2;
34 u32 uid0;
35 u32 uid1;
36 u32 uid2;
37};
38
39struct stm32_rcc_regs {
40 u32 cr; /* RCC clock control */
41 u32 cfgr; /* RCC clock configuration */
42 u32 cir; /* RCC clock interrupt */
43 u32 apb2rstr; /* RCC APB2 peripheral reset */
44 u32 apb1rstr; /* RCC APB1 peripheral reset */
45 u32 ahbenr; /* RCC AHB peripheral clock enable */
46 u32 apb2enr; /* RCC APB2 peripheral clock enable */
47 u32 apb1enr; /* RCC APB1 peripheral clock enable */
48 u32 bdcr; /* RCC Backup domain control */
49 u32 csr; /* RCC clock control & status */
50};
51
52struct stm32_pwr_regs {
53 u32 cr;
54 u32 csr;
55};
56
57struct stm32_flash_regs {
58 u32 acr;
59 u32 keyr;
60 u32 optkeyr;
61 u32 sr;
62 u32 cr;
63 u32 ar;
64 u32 rsvd1; /* Reserved */
65 u32 obr;
66 u32 wrpr;
67 u32 rsvd2[8]; /* Reserved */
68 u32 keyr2;
69 u32 rsvd3;
70 u32 sr2;
71 u32 cr2;
72 u32 ar2;
73};
74
75/* Per bank register set for XL devices */
76struct stm32_flash_bank_regs {
77 u32 keyr;
78 u32 rsvd; /* Reserved */
79 u32 sr;
80 u32 cr;
81 u32 ar;
82};
83
84/*
85 * Registers access macros
86 */
87#define STM32_DES_BASE (0x1ffff7e0)
88#define STM32_DES ((struct stm32_des_regs *)STM32_DES_BASE)
89
90#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x9000)
91#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
92
93#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
94#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
95
96#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0xa000)
97#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE)
98
99#define STM32_FLASH_SR_BSY (1 << 0)
100
101#define STM32_FLASH_CR_PG (1 << 0)
102#define STM32_FLASH_CR_PER (1 << 1)
103#define STM32_FLASH_CR_STRT (1 << 6)
104#define STM32_FLASH_CR_LOCK (1 << 7)
105
106enum clock {
107 CLOCK_CORE,
108 CLOCK_AHB,
109 CLOCK_APB1,
110 CLOCK_APB2
111};
112
113int configure_clocks(void);
114unsigned long clock_get(enum clock clck);
115
116#endif /* _MACH_STM32_H_ */