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git01.mediatek.com / filogic / uboot / 88459d369edda1503aa5767f2055d1c232335c16 / . / board / xilinx / zynqmp / zynqmp-sm-k24-revA / psu_init_gpl.c
blob: 274203ffaa3b147977bffeff222ccda31df2453d [file] [log] [blame]
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
4 */
5
6#include <asm/arch/psu_init_gpl.h>
7#include <xil_io.h>
8
9static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly,
10 int d_lock_cnt, int d_lfhf, int d_cp, int d_res)
11{
12 unsigned int pll_ctrl_regval;
13 unsigned int pll_status_regval;
14
15 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
16 pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
17 pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
18 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
19
20 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
21 pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
22 pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
23 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
24
25 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
26 pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
27 pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
28 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
29
30 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
31 pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
32 pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
33 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
34
35 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
36 pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
37 pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
38 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
39
40 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
41 pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
42 pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
43 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
44
45 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
46 pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
47 pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
48 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
49
50 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
51 pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
52 pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
53 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
54
55 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
56 pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
57 pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
58 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
59
60 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
61 pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
62 pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
63 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
64
65 pll_status_regval = 0x00000000;
66 while ((pll_status_regval & 0x00000002U) != 0x00000002U)
67 pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
68
69 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
70 pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
71 pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
72 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
73}
74
75static unsigned long psu_pll_init_data(void)
76{
77 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
78 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
79 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
80 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
81 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
82 mask_poll(0xFF5E0040, 0x00000002U);
83 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
84 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
85 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
86 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
87 psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
88 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
89 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
90 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
91 mask_poll(0xFF5E0040, 0x00000001U);
92 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
93 psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
94 psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
95 psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014F00U);
96 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
97 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
98 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
99 mask_poll(0xFD1A0044, 0x00000001U);
100 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
101 psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
102 psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x8000FB15U);
103 psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
104 psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
105 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
106 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
107 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
108 mask_poll(0xFD1A0044, 0x00000002U);
109 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
110 psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
111 psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
112 psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
113 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
114 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
115 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
116 mask_poll(0xFD1A0044, 0x00000004U);
117 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
118 psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
119
120 return 1;
121}
122
123static unsigned long psu_clock_init_data(void)
124{
125 psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
126 psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
127 psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
128 psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
129 psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
130 psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
131 psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
132 psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
133 psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
134 psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
135 psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000200U);
136 psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
137 psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
138 psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
139 psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
140 psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
141 psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
142 psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
143 psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
144 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
145 psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
146 psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
147 psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
148 psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011603U);
149 psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011403U);
150 psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
151 psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
152 psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
153 psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
154 psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
155 psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000300U);
156 psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
157 psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
158 psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
159 psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
160 psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
161 psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
162 psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
163
164 return 1;
165}
166
167static unsigned long psu_ddr_init_data(void)
168{
169 psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
170 psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
171 psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
172 psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
173 psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00501B9BU);
174 psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
175 psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
176 psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
177 psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
178 psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
179 psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00408093U);
180 psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
181 psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
182 psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
183 psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
184 psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030403U);
185 psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00680000U);
186 psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
187 psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x0034001BU);
188 psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
189 psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
190 psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
191 psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
192 psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
193 psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
194 psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x13151117U);
195 psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
196 psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x050A170FU);
197 psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
198 psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
199 psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
200 psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
201 psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
202 psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
203 psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
204 psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
205 psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
206 psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x820D0010U);
207 psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B64228U);
208 psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04918208U);
209 psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
210 psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
211 psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
212 psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
213 psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
214 psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
215 psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000F06U);
216 psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
217 psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
218 psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
219 psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
220 psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
221 psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
222 psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
223 psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
224 psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
225 psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
226 psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
227 psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
228 psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
229 psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
230 psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
231 psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
232 psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
233 psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
234 psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
235 psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
236 psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
237 psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
238 psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
239 psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
240 psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
241 psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
242 psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
243 psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
244 psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
245 psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
246 psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
247 psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
248 psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
249 psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
250 psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
251 psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
252 psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
253 psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
254 psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
255 psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
256 psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
257 psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
258 psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
259 psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
260 psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
261 psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
262 psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
263 psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
264 psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
265 psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
266 psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
267 psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
268 psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
269 psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
270 psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
271 psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
272 psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
273 psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
274 psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
275 psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
276 psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
277 psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
278 psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
279 psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
280 psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
281 psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
282 psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
283 psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
284 psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
285 psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
286 psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
287 psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07C30U);
288 psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
289 psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
290 psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
291 psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
292 psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
293 psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
294 psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
295 psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E5U);
296 psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
297 psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
298 psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282A0711U);
299 psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F012EU);
300 psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
301 psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01262B0BU);
302 psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0043260BU);
303 psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A14U);
304 psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
305 psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
306 psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
307 psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
308 psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
309 psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000034U);
310 psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x0000001BU);
311 psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
312 psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
313 psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
314 psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
315 psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
316 psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U);
317 psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
318 psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
319 psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
320 psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
321 psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
322 psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
323 psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
324 psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
325 psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
326 psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
327 psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
328 psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
329 psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
330 psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
331 psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
332 psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
333 psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
334 psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
335 psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
336 psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
337 psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
338 psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
339 psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8C58U);
340 psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
341 psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
342 psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
343 psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
344 psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
345 psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
346 psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
347 psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
348 psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
349 psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
350 psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
351 psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
352 psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
353 psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
354 psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
355 psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
356 psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
357 psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
358 psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
359 psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U);
360 psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
361 psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
362 psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
363 psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
364 psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
365 psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U);
366 psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
367 psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
368 psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
369 psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
370 psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
371 psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U);
372 psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
373 psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
374 psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
375 psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
376 psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
377 psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
378 psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
379 psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
380 psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
381 psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
382 psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
383 psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
384 psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
385 psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
386 psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
387 psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
388 psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
389 psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
390 psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
391 psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
392 psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
393 psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
394 psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
395 psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
396 psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
397 psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
398 psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
399 psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
400 psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
401 psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
402 psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
403 psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
404 psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
405 psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
406 psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
407 psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
408 psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
409 psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
410 psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
411 psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
412 psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
413 psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
414 psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
415 psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
416 psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
417 psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
418 psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
419 psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
420 psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
421 psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
422 psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
423 psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
424 psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
425 psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
426 psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
427 psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
428 psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
429
430 return 1;
431}
432
433static unsigned long psu_ddr_qos_init_data(void)
434{
435 psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
436 psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
437 psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
438 psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
439 psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
440 psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
441 psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
442 psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
443 psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
444 psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
445 psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
446 psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
447 psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
448 psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
449
450 return 1;
451}
452
453static unsigned long psu_mio_init_data(void)
454{
455 psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
456 psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
457 psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
458 psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
459 psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
460 psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
461 psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U);
462 psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
463 psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
464 psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U);
465 psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U);
466 psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U);
467 psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
468 psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
469 psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U);
470 psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U);
471 psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U);
472 psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
473 psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
474 psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
475 psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
476 psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
477 psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
478 psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
479 psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
480 psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
481 psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
482 psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
483 psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
484 psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
485 psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
486 psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
487 psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
488 psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
489 psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
490 psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
491 psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U);
492 psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U);
493 psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
494 psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
495 psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
496 psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
497 psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
498 psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
499 psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
500 psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
501 psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
502 psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
503 psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
504 psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
505 psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
506 psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
507 psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
508 psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
509 psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
510 psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
511 psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
512 psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
513 psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
514 psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
515 psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
516 psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
517 psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
518 psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
519 psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
520 psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
521 psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
522 psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
523 psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
524 psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
525 psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
526 psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
527 psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
528 psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
529 psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
530 psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
Neal Frager31e77672024-06-04 09:38:54 +0100[diff] [blame]531 psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
532 psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]533 psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
534 psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U);
535 psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
536 psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x00000000U);
537 psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
538 psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
539 psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
540 psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
541 psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU);
542 psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x00080814U);
543 psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
544 psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
545 psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
546 psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
547 psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F7F7EBU);
548 psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x00FC000BU);
549 psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
550 psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
551 psu_mask_write(0xFF18017C, 0x0357FFFFU, 0x0357FFFFU);
552 psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU);
553 psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x0303FFF4U);
554 psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
555
556 return 1;
557}
558
559static unsigned long psu_peripherals_pre_init_data(void)
560{
561 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
562 psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
563
564 return 1;
565}
566
567static unsigned long psu_peripherals_init_data(void)
568{
569 psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U);
570 psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
571 psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
Neal Frager31e77672024-06-04 09:38:54 +0100[diff] [blame]572 psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]573 psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
574 psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
575 psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
Neal Frager31e77672024-06-04 09:38:54 +0100[diff] [blame]576 psu_mask_write(0xFF5E0238, 0x00000080U, 0x00000000U);
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]577 psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
578 psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
579 psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U);
580 psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
Neal Frager31e77672024-06-04 09:38:54 +0100[diff] [blame]581 psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]582 psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
583 psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
584 psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
585 psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
586 psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
587 psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
588 psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
Neal Frager31e77672024-06-04 09:38:54 +0100[diff] [blame]589 psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x01000000U);
590 psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x01000000U);
591 psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U);
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]592
593 mask_delay(1);
Neal Frager31e77672024-06-04 09:38:54 +0100[diff] [blame]594 psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0000U);
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]595
596 mask_delay(5);
Neal Frager31e77672024-06-04 09:38:54 +0100[diff] [blame]597 psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U);
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]598
599 return 1;
600}
601
Michal Simek72b232f2023-01-18 13:11:59 +0100[diff] [blame]602static unsigned long psu_afi_config(void)
603{
604 psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
605 psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
606
607 return 1;
608}
609
610static unsigned long psu_ddr_phybringup_data(void)
611{
612 unsigned int regval = 0;
613
614 for (int tp = 0; tp < 20; tp++)
615 regval = Xil_In32(0xFD070018);
616 int cur_PLLCR0;
617
618 cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
619 int cur_DX8SL0PLLCR0;
620
621 cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
622 int cur_DX8SL1PLLCR0;
623
624 cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
625 int cur_DX8SL2PLLCR0;
626
627 cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
628 int cur_DX8SL3PLLCR0;
629
630 cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
631 int cur_DX8SL4PLLCR0;
632
633 cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
634 int cur_DX8SLBPLLCR0;
635
636 cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
637 Xil_Out32(0xFD080068, 0x02120000);
638 Xil_Out32(0xFD081404, 0x02120000);
639 Xil_Out32(0xFD081444, 0x02120000);
640 Xil_Out32(0xFD081484, 0x02120000);
641 Xil_Out32(0xFD0814C4, 0x02120000);
642 Xil_Out32(0xFD081504, 0x02120000);
643 Xil_Out32(0xFD0817C4, 0x02120000);
644 int cur_div2;
645
646 cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U;
647 int cur_fbdiv;
648
649 cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
650 dpll_prog(1, 49, 63, 625, 3, 3, 2);
651 for (int tp = 0; tp < 20; tp++)
652 regval = Xil_In32(0xFD070018);
653 unsigned int pll_retry = 10;
654 unsigned int pll_locked = 0;
655
656 while ((pll_retry > 0) && (!pll_locked)) {
657 Xil_Out32(0xFD080004, 0x00040010);
658 Xil_Out32(0xFD080004, 0x00040011);
659
660 while ((Xil_In32(0xFD080030) & 0x1) != 1)
661 ;
662 pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
663 >> 31;
664 pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
665 >> 16;
666 pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
667 pll_retry--;
668 }
669 Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
670 if (!pll_locked)
671 return 0;
672
673 Xil_Out32(0xFD080004U, 0x00040063U);
674 Xil_Out32(0xFD0800C0U, 0x00000001U);
675
676 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
677 ;
678 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
679
680 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
681 ;
682 Xil_Out32(0xFD070010U, 0x80000018U);
683 Xil_Out32(0xFD0701B0U, 0x00000005U);
684 regval = Xil_In32(0xFD070018);
685 while ((regval & 0x1) != 0x0)
686 regval = Xil_In32(0xFD070018);
687
688 regval = Xil_In32(0xFD070018);
689 regval = Xil_In32(0xFD070018);
690 regval = Xil_In32(0xFD070018);
691 regval = Xil_In32(0xFD070018);
692 regval = Xil_In32(0xFD070018);
693 regval = Xil_In32(0xFD070018);
694 regval = Xil_In32(0xFD070018);
695 regval = Xil_In32(0xFD070018);
696 regval = Xil_In32(0xFD070018);
697 regval = Xil_In32(0xFD070018);
698 Xil_Out32(0xFD070014U, 0x00000331U);
699 Xil_Out32(0xFD070010U, 0x80000018U);
700 regval = Xil_In32(0xFD070018);
701 while ((regval & 0x1) != 0x0)
702 regval = Xil_In32(0xFD070018);
703
704 regval = Xil_In32(0xFD070018);
705 regval = Xil_In32(0xFD070018);
706 regval = Xil_In32(0xFD070018);
707 regval = Xil_In32(0xFD070018);
708 regval = Xil_In32(0xFD070018);
709 regval = Xil_In32(0xFD070018);
710 regval = Xil_In32(0xFD070018);
711 regval = Xil_In32(0xFD070018);
712 regval = Xil_In32(0xFD070018);
713 regval = Xil_In32(0xFD070018);
714 Xil_Out32(0xFD070014U, 0x00000B36U);
715 Xil_Out32(0xFD070010U, 0x80000018U);
716 regval = Xil_In32(0xFD070018);
717 while ((regval & 0x1) != 0x0)
718 regval = Xil_In32(0xFD070018);
719
720 regval = Xil_In32(0xFD070018);
721 regval = Xil_In32(0xFD070018);
722 regval = Xil_In32(0xFD070018);
723 regval = Xil_In32(0xFD070018);
724 regval = Xil_In32(0xFD070018);
725 regval = Xil_In32(0xFD070018);
726 regval = Xil_In32(0xFD070018);
727 regval = Xil_In32(0xFD070018);
728 regval = Xil_In32(0xFD070018);
729 regval = Xil_In32(0xFD070018);
730 Xil_Out32(0xFD070014U, 0x00000C56U);
731 Xil_Out32(0xFD070010U, 0x80000018U);
732 regval = Xil_In32(0xFD070018);
733 while ((regval & 0x1) != 0x0)
734 regval = Xil_In32(0xFD070018);
735
736 regval = Xil_In32(0xFD070018);
737 regval = Xil_In32(0xFD070018);
738 regval = Xil_In32(0xFD070018);
739 regval = Xil_In32(0xFD070018);
740 regval = Xil_In32(0xFD070018);
741 regval = Xil_In32(0xFD070018);
742 regval = Xil_In32(0xFD070018);
743 regval = Xil_In32(0xFD070018);
744 regval = Xil_In32(0xFD070018);
745 regval = Xil_In32(0xFD070018);
746 Xil_Out32(0xFD070014U, 0x00000E19U);
747 Xil_Out32(0xFD070010U, 0x80000018U);
748 regval = Xil_In32(0xFD070018);
749 while ((regval & 0x1) != 0x0)
750 regval = Xil_In32(0xFD070018);
751
752 regval = Xil_In32(0xFD070018);
753 regval = Xil_In32(0xFD070018);
754 regval = Xil_In32(0xFD070018);
755 regval = Xil_In32(0xFD070018);
756 regval = Xil_In32(0xFD070018);
757 regval = Xil_In32(0xFD070018);
758 regval = Xil_In32(0xFD070018);
759 regval = Xil_In32(0xFD070018);
760 regval = Xil_In32(0xFD070018);
761 regval = Xil_In32(0xFD070018);
762 Xil_Out32(0xFD070014U, 0x00001616U);
763 Xil_Out32(0xFD070010U, 0x80000018U);
764 Xil_Out32(0xFD070010U, 0x80000010U);
765 Xil_Out32(0xFD0701B0U, 0x00000005U);
766 Xil_Out32(0xFD070320U, 0x00000001U);
767 while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
768 ;
769 prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
770 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
771 prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
772 prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
773 prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
774 prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
775 prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
776 prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
777 for (int tp = 0; tp < 20; tp++)
778 regval = Xil_In32(0xFD070018);
779
780 Xil_Out32(0xFD080068, cur_PLLCR0);
781 Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
782 Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
783 Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
784 Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
785 Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
786 Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
787 for (int tp = 0; tp < 20; tp++)
788 regval = Xil_In32(0xFD070018);
789
790 dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2);
791 for (int tp = 0; tp < 2000; tp++)
792 regval = Xil_In32(0xFD070018);
793
794 prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
795 prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
796 prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
797 prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
798 prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
799 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
800
801 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
802 ;
803 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
804
805 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
806 ;
807 for (int tp = 0; tp < 2000; tp++)
808 regval = Xil_In32(0xFD070018);
809
810 prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
811 prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
812 prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
813 prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
814 prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
815 for (int tp = 0; tp < 2000; tp++)
816 regval = Xil_In32(0xFD070018);
817
818 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
819 Xil_Out32(0xFD080004, 0x0014FE01);
820
821 regval = Xil_In32(0xFD080030);
822 while (regval != 0x8000007E)
823 regval = Xil_In32(0xFD080030);
824
825 Xil_Out32(0xFD080200U, 0x000091C7U);
826 regval = Xil_In32(0xFD080030);
827 while (regval != 0x80008FFF)
828 regval = Xil_In32(0xFD080030);
829
830 Xil_Out32(0xFD080200U, 0x800091C7U);
831 regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
832 if (regval != 0)
833 return 0;
834
835 Xil_Out32(0xFD080200U, 0x800091C7U);
836 int cur_R006_tREFPRD;
837
838 cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
839 prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
840
841 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
842 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
843 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
844 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
845 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
846 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
847
848 Xil_Out32(0xFD080004, 0x00060001);
849 regval = Xil_In32(0xFD080030);
850 while ((regval & 0x80004001) != 0x80004001)
851 regval = Xil_In32(0xFD080030);
852
853 regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
854 if (regval != 0)
855 return 0;
856
857 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
858 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
859 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
860 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
861 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
862 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
863
864 Xil_Out32(0xFD080200U, 0x800091C7U);
865 prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
866
867 Xil_Out32(0xFD080004, 0x0000C001);
868 regval = Xil_In32(0xFD080030);
869 while ((regval & 0x80000C01) != 0x80000C01)
870 regval = Xil_In32(0xFD080030);
871
872 prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
873 prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
874 prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
875 prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
876 Xil_Out32(0xFD070180U, 0x020D0010U);
877 Xil_Out32(0xFD070060U, 0x00000000U);
878 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
879 for (int tp = 0; tp < 4000; tp++)
880 regval = Xil_In32(0xFD070018);
881
882 prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
883 prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
884 prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
885 prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
886 prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
887 prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
888 prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
889 prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
890 prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
891 prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
892 prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
893 prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
894 prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
895 prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
896 prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
897 prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
898 prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
899 prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
900 prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
901 prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
902 prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
903 prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
904 prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
905 prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
906 prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
907
908 return 1;
909}
910
911static void init_peripheral(void)
912{
913 psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
914}
915
916int psu_init(void)
917{
918 int status = 1;
919
920 status &= psu_mio_init_data();
921 status &= psu_peripherals_pre_init_data();
922 status &= psu_pll_init_data();
923 status &= psu_clock_init_data();
924 status &= psu_ddr_init_data();
925 status &= psu_ddr_phybringup_data();
926 status &= psu_peripherals_init_data();
927 init_peripheral();
928
929 status &= psu_afi_config();
930 psu_ddr_qos_init_data();
931
932 if (status == 0)
933 return 1;
934 return 0;
935}