blob: 7affd11d2ff25902a18d956710d94e62fcdea622 [file] [log] [blame]
Simon Glassefad57f2015-08-30 16:55:33 -06001/*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
10#include <reset.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/cru_rk3288.h>
14#include <asm/arch/hardware.h>
15#include <linux/err.h>
16
17int rk3288_reset_request(struct udevice *dev, enum reset_t type)
18{
19 struct rk3288_cru *cru = rockchip_get_cru();
20
21 if (IS_ERR(cru))
22 return PTR_ERR(cru);
23 switch (type) {
24 case RESET_WARM:
25 writel(RK_CLRBITS(0xffff), &cru->cru_mode_con);
26 writel(0xeca8, &cru->cru_glb_srst_snd_value);
27 break;
28 case RESET_COLD:
29 writel(RK_CLRBITS(0xffff), &cru->cru_mode_con);
30 writel(0xfdb9, &cru->cru_glb_srst_fst_value);
31 break;
32 default:
33 return -EPROTONOSUPPORT;
34 }
35
36 return -EINPROGRESS;
37}
38
39static struct reset_ops rk3288_reset = {
40 .request = rk3288_reset_request,
41};
42
43U_BOOT_DRIVER(reset_rk3288) = {
44 .name = "rk3288_reset",
45 .id = UCLASS_RESET,
46 .ops = &rk3288_reset,
47};