Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Sentec Cobra Board. |
| 4 | * |
| 5 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* --- |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 9 | * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 10 | * Date: 2004-03-29 |
| 11 | * Author: Florian Schlote |
| 12 | * |
| 13 | * For a description of configuration options please refer also to the |
| 14 | * general u-boot-1.x.x/README file |
| 15 | * --- |
| 16 | */ |
| 17 | |
| 18 | /* --- |
| 19 | * board/config.h - configuration options, board specific |
| 20 | * --- |
| 21 | */ |
| 22 | |
| 23 | #ifndef _CONFIG_COBRA5272_H |
| 24 | #define _CONFIG_COBRA5272_H |
| 25 | |
| 26 | /* --- |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 27 | * Defines processor clock - important for correct timings concerning serial |
| 28 | * interface etc. |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 29 | * --- |
| 30 | */ |
| 31 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 32 | #define CFG_SYS_CLK 66000000 |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 33 | #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 34 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 35 | /* --- |
| 36 | * Define baudrate for UART1 (console output, tftp, ...) |
| 37 | * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 38 | * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 39 | * interface |
| 40 | * --- |
| 41 | */ |
| 42 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 43 | #define CFG_SYS_UART_PORT (0) |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 44 | |
| 45 | /* --- |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 46 | * Configuration for environment |
| 47 | * Environment is embedded in u-boot in the second sector of the flash |
| 48 | * --- |
| 49 | */ |
| 50 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 51 | #define LDS_BOARD_TEXT \ |
Simon Glass | 547cb40 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 52 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 53 | env/embedded.o(.text); |
Jon Loeliger | 37ec35e | 2007-07-04 22:31:56 -0500 | [diff] [blame] | 54 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 55 | /* |
| 56 | *----------------------------------------------------------------------------- |
| 57 | * Define user parameters that have to be customized most likely |
| 58 | *----------------------------------------------------------------------------- |
| 59 | */ |
| 60 | |
| 61 | /*AUTOBOOT settings - booting images automatically by u-boot after power on*/ |
| 62 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 63 | /* The following settings will be contained in the environment block ; if you |
| 64 | want to use a neutral environment all those settings can be manually set in |
| 65 | u-boot: 'set' command */ |
| 66 | |
| 67 | #if 0 |
| 68 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 69 | enter a valid image address in flash */ |
| 70 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 71 | /* User network settings */ |
| 72 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 73 | #endif |
| 74 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 75 | /*---*/ |
| 76 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 77 | /* |
| 78 | *----------------------------------------------------------------------------- |
| 79 | * End of user parameters to be customized |
| 80 | *----------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | /* --- |
| 84 | * Defines memory range for test |
| 85 | * --- |
| 86 | */ |
| 87 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 88 | /* --- |
| 89 | * Low Level Configuration Settings |
| 90 | * (address mappings, register initial values, etc.) |
| 91 | * You should know what you are doing if you make changes here. |
| 92 | * --- |
| 93 | */ |
| 94 | |
| 95 | /* --- |
| 96 | * Base register address |
| 97 | * --- |
| 98 | */ |
| 99 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 100 | #define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 101 | |
| 102 | /* --- |
| 103 | * System Conf. Reg. & System Protection Reg. |
| 104 | * --- |
| 105 | */ |
| 106 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 107 | #define CFG_SYS_SCR 0x0003 |
| 108 | #define CFG_SYS_SPR 0xffff |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 109 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 110 | /*----------------------------------------------------------------------- |
| 111 | * Definitions for initial stack pointer and data area (in internal SRAM) |
| 112 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 113 | #define CFG_SYS_INIT_RAM_ADDR 0x20000000 |
| 114 | #define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 115 | |
| 116 | /*----------------------------------------------------------------------- |
| 117 | * Start addresses for the final memory configuration |
| 118 | * (Set up by the startup code) |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 119 | * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 120 | */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 121 | #define CFG_SYS_SDRAM_BASE 0x00000000 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 122 | |
| 123 | /* |
| 124 | *------------------------------------------------------------------------- |
| 125 | * RAM SIZE (is defined above) |
| 126 | *----------------------------------------------------------------------- |
| 127 | */ |
| 128 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 129 | /* #define CFG_SYS_SDRAM_SIZE 16 */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 130 | |
| 131 | /* |
| 132 | *----------------------------------------------------------------------- |
| 133 | */ |
| 134 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 135 | #define CFG_SYS_FLASH_BASE 0xffe00000 |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 136 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 137 | /* |
| 138 | * For booting Linux, the board info and command line data |
| 139 | * have to be in the first 8 MB of memory, since this is |
| 140 | * the maximum mapped by the Linux kernel during initialization ?? |
| 141 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 142 | #define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 143 | |
| 144 | /*----------------------------------------------------------------------- |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 145 | * Cache Configuration |
| 146 | */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 147 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 148 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 149 | CFG_SYS_INIT_RAM_SIZE - 8) |
| 150 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
| 151 | CFG_SYS_INIT_RAM_SIZE - 4) |
| 152 | #define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
| 153 | #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 154 | CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 155 | CF_ACR_EN | CF_ACR_SM_ALL) |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 156 | #define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 157 | CF_CACR_DISD | CF_CACR_INVI | \ |
| 158 | CF_CACR_CEIB | CF_CACR_DCM | \ |
| 159 | CF_CACR_EUSP) |
| 160 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 161 | /*----------------------------------------------------------------------- |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 162 | * LED config |
| 163 | */ |
| 164 | #define LED_STAT_0 0xffff /*all LEDs off*/ |
| 165 | #define LED_STAT_1 0xfffe |
| 166 | #define LED_STAT_2 0xfffd |
| 167 | #define LED_STAT_3 0xfffb |
| 168 | #define LED_STAT_4 0xfff7 |
| 169 | #define LED_STAT_5 0xffef |
| 170 | #define LED_STAT_6 0xffdf |
| 171 | #define LED_STAT_7 0xff00 /*all LEDs on*/ |
| 172 | |
| 173 | /*----------------------------------------------------------------------- |
| 174 | * Port configuration (GPIO) |
| 175 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 176 | #define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 177 | GPIO*/ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 178 | #define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 179 | (1^=output, 0^=input) */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 180 | #define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ |
| 181 | #define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 182 | configuration */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 183 | #define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ |
| 184 | #define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */ |
| 185 | #define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */ |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 186 | |
Angelo Dureghello | 49becce | 2023-02-25 23:25:26 +0100 | [diff] [blame] | 187 | |
wdenk | c4cbd34 | 2005-01-09 18:21:42 +0000 | [diff] [blame] | 188 | #endif /* _CONFIG_COBRA5272_H */ |