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git01.mediatek.com / filogic / uboot / 879d2fb3431bc7babeaeeb5a751082efcb5ca45f / . / arch / arm / include / asm / arch-rockchip / cru_rk3128.h
blob: 90012c7fce0521ecb8dabd33712ca5b9f6793f6d [file] [log] [blame]
Kever Yang1650a682017-11-28 16:04:17 +0800[diff] [blame]1/*
2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _ASM_ARCH_CRU_RK3128_H
8#define _ASM_ARCH_CRU_RK3128_H
9
10#include <common.h>
11
12#define MHz 1000000
13#define OSC_HZ (24 * MHz)
14
15#define APLL_HZ (600 * MHz)
16#define GPLL_HZ (594 * MHz)
17
18#define CORE_PERI_HZ 150000000
19#define CORE_ACLK_HZ 300000000
20
21#define BUS_ACLK_HZ 148500000
22#define BUS_HCLK_HZ 148500000
23#define BUS_PCLK_HZ 74250000
24
25#define PERI_ACLK_HZ 148500000
26#define PERI_HCLK_HZ 148500000
27#define PERI_PCLK_HZ 74250000
28
29/* Private data for the clock driver - used by rockchip_get_cru() */
30struct rk3128_clk_priv {
31 struct rk3128_cru *cru;
32};
33
34struct rk3128_cru {
35 struct rk3128_pll {
36 unsigned int con0;
37 unsigned int con1;
38 unsigned int con2;
39 unsigned int con3;
40 } pll[4];
41 unsigned int cru_mode_con;
42 unsigned int cru_clksel_con[35];
43 unsigned int cru_clkgate_con[11];
44 unsigned int reserved;
45 unsigned int cru_glb_srst_fst_value;
46 unsigned int cru_glb_srst_snd_value;
47 unsigned int reserved1[2];
48 unsigned int cru_softrst_con[9];
49 unsigned int cru_misc_con;
50 unsigned int reserved2[2];
51 unsigned int cru_glb_cnt_th;
52 unsigned int reserved3[3];
53 unsigned int cru_glb_rst_st;
54 unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
55 unsigned int cru_sdmmc_con[2];
56 unsigned int cru_sdio_con[2];
57 unsigned int reserved5[2];
58 unsigned int cru_emmc_con[2];
59 unsigned int reserved6[4];
60 unsigned int cru_pll_prg_en;
61};
62check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
63
64struct pll_div {
65 u32 refdiv;
66 u32 fbdiv;
67 u32 postdiv1;
68 u32 postdiv2;
69 u32 frac;
70};
71
72enum {
73 /* PLLCON0*/
74 PLL_POSTDIV1_SHIFT = 12,
75 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
76 PLL_FBDIV_SHIFT = 0,
77 PLL_FBDIV_MASK = 0xfff,
78
79 /* PLLCON1 */
80 PLL_RST_SHIFT = 14,
81 PLL_PD_SHIFT = 13,
82 PLL_PD_MASK = 1 << PLL_PD_SHIFT,
83 PLL_DSMPD_SHIFT = 12,
84 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
85 PLL_LOCK_STATUS_SHIFT = 10,
86 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
87 PLL_POSTDIV2_SHIFT = 6,
88 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
89 PLL_REFDIV_SHIFT = 0,
90 PLL_REFDIV_MASK = 0x3f,
91
92 /* CRU_MODE */
93 GPLL_MODE_SHIFT = 12,
94 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
95 GPLL_MODE_SLOW = 0,
96 GPLL_MODE_NORM,
97 GPLL_MODE_DEEP,
98 CPLL_MODE_SHIFT = 8,
99 CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
100 CPLL_MODE_SLOW = 0,
101 CPLL_MODE_NORM,
102 DPLL_MODE_SHIFT = 4,
103 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
104 DPLL_MODE_SLOW = 0,
105 DPLL_MODE_NORM,
106 APLL_MODE_SHIFT = 0,
107 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
108 APLL_MODE_SLOW = 0,
109 APLL_MODE_NORM,
110
111 /* CRU_CLK_SEL0_CON */
112 BUS_ACLK_PLL_SEL_SHIFT = 14,
113 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
114 BUS_ACLK_PLL_SEL_CPLL = 0,
115 BUS_ACLK_PLL_SEL_GPLL,
116 BUS_ACLK_PLL_SEL_GPLL_DIV2,
117 BUS_ACLK_PLL_SEL_GPLL_DIV3,
118 BUS_ACLK_DIV_SHIFT = 8,
119 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
120 CORE_CLK_PLL_SEL_SHIFT = 7,
121 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
122 CORE_CLK_PLL_SEL_APLL = 0,
123 CORE_CLK_PLL_SEL_GPLL_DIV2,
124 CORE_DIV_CON_SHIFT = 0,
125 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
126
127 /* CRU_CLK_SEL1_CON */
128 BUS_PCLK_DIV_SHIFT = 12,
129 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
130 BUS_HCLK_DIV_SHIFT = 8,
131 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
132 CORE_ACLK_DIV_SHIFT = 4,
133 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
134 CORE_PERI_DIV_SHIFT = 0,
135 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
136
137 /* CRU_CLK_SEL2_CON */
138 NANDC_PLL_SEL_SHIFT = 14,
Philipp Tomsichf16060e2017-12-02 00:14:55 +0100[diff] [blame]139 NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
Kever Yang1650a682017-11-28 16:04:17 +0800[diff] [blame]140 NANDC_PLL_SEL_CPLL = 0,
141 NANDC_PLL_SEL_GPLL,
142 NANDC_CLK_DIV_SHIFT = 8,
143 NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT,
144 PVTM_CLK_DIV_SHIFT = 0,
145 PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT,
146
147 /* CRU_CLKSEL10_CON */
148 PERI_PLL_SEL_SHIFT = 14,
149 PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT,
150 PERI_PLL_APLL = 0,
151 PERI_PLL_DPLL,
152 PERI_PLL_GPLL,
153 PERI_PCLK_DIV_SHIFT = 12,
154 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
155 PERI_HCLK_DIV_SHIFT = 8,
156 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
157 PERI_ACLK_DIV_SHIFT = 0,
158 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
159
160 /* CRU_CLKSEL11_CON */
161 MMC0_PLL_SHIFT = 6,
162 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
163 MMC0_SEL_APLL = 0,
164 MMC0_SEL_GPLL,
165 MMC0_SEL_GPLL_DIV2,
166 MMC0_SEL_24M,
167 MMC0_DIV_SHIFT = 0,
168 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
169
170 /* CRU_CLKSEL12_CON */
171 EMMC_PLL_SHIFT = 14,
172 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
173 EMMC_SEL_APLL = 0,
174 EMMC_SEL_GPLL,
175 EMMC_SEL_GPLL_DIV2,
176 EMMC_SEL_24M,
177 EMMC_DIV_SHIFT = 8,
178 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
179
180 /* CLKSEL_CON24 */
181 SARADC_DIV_CON_SHIFT = 8,
182 SARADC_DIV_CON_MASK = GENMASK(15, 8),
183 SARADC_DIV_CON_WIDTH = 8,
184
185 /* CRU_CLKSEL27_CON*/
186 DCLK_VOP_SEL_SHIFT = 0,
187 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
188 DCLK_VOP_PLL_SEL_CPLL = 0,
189 DCLK_VOP_DIV_CON_SHIFT = 8,
Philipp Tomsich4703ea62017-12-02 00:19:14 +0100[diff] [blame]190 DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
Kever Yang1650a682017-11-28 16:04:17 +0800[diff] [blame]191
192 /* CRU_CLKSEL31_CON */
193 VIO0_PLL_SHIFT = 5,
194 VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT,
195 VI00_SEL_CPLL = 0,
196 VIO0_SEL_GPLL,
197 VIO0_DIV_SHIFT = 0,
198 VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT,
199 VIO1_PLL_SHIFT = 13,
200 VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT,
201 VI01_SEL_CPLL = 0,
202 VIO1_SEL_GPLL,
203 VIO1_DIV_SHIFT = 8,
204 VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT,
205
206 /* CRU_SOFTRST5_CON */
207 DDRCTRL_PSRST_SHIFT = 11,
208 DDRCTRL_SRST_SHIFT = 10,
209 DDRPHY_PSRST_SHIFT = 9,
210 DDRPHY_SRST_SHIFT = 8,
211};
212#endif