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git01.mediatek.com / filogic / uboot / 8780ada81742a073085e0c97dee8f99be94ae0cf / . / arch / arm / dts / sun50i-h616-orangepi-zero2.dts
blob: d83852e72f063488d5fa50e93de3cb4adf08451c [file] [log] [blame]
Andre Przywara8780ada2023-10-19 15:51:39 +0100[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]2/*
3 * Copyright (C) 2020 Arm Ltd.
4 */
5
6/dts-v1/;
7
Andre Przywara8780ada2023-10-19 15:51:39 +0100[diff] [blame^]8#include "sun50i-h616-orangepi-zero.dtsi"
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]9
10/ {
11 model = "OrangePi Zero2";
12 compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]13};
14
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]15&emac0 {
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]16 phy-supply = <&reg_dcdce>;
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]17};
18
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]19&mmc0 {
20 vmmc-supply = <&reg_dcdce>;
Andre Przywaraed2724b2023-01-12 11:22:20 +0000[diff] [blame]21};
22
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]23&r_rsb {
24 status = "okay";
25
26 axp305: pmic@745 {
27 compatible = "x-powers,axp305", "x-powers,axp805",
28 "x-powers,axp806";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 reg = <0x745>;
32
33 x-powers,self-working-mode;
34 vina-supply = <&reg_vcc5v>;
35 vinb-supply = <&reg_vcc5v>;
36 vinc-supply = <&reg_vcc5v>;
37 vind-supply = <&reg_vcc5v>;
38 vine-supply = <&reg_vcc5v>;
39 aldoin-supply = <&reg_vcc5v>;
40 bldoin-supply = <&reg_vcc5v>;
41 cldoin-supply = <&reg_vcc5v>;
42
43 regulators {
44 reg_aldo1: aldo1 {
45 regulator-always-on;
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 regulator-name = "vcc-sys";
49 };
50
51 reg_aldo2: aldo2 { /* 3.3V on headers */
52 regulator-always-on;
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 regulator-name = "vcc3v3-ext";
56 };
57
58 reg_aldo3: aldo3 { /* 3.3V on headers */
59 regulator-always-on;
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 regulator-name = "vcc3v3-ext2";
63 };
64
65 reg_bldo1: bldo1 {
66 regulator-always-on;
67 regulator-min-microvolt = <1800000>;
68 regulator-max-microvolt = <1800000>;
69 regulator-name = "vcc1v8";
70 };
71
72 bldo2 {
73 /* unused */
74 };
75
76 bldo3 {
77 /* unused */
78 };
79
80 bldo4 {
81 /* unused */
82 };
83
84 cldo1 {
85 /* reserved */
86 };
87
88 cldo2 {
89 /* unused */
90 };
91
92 cldo3 {
93 /* unused */
94 };
95
96 reg_dcdca: dcdca {
97 regulator-always-on;
98 regulator-min-microvolt = <810000>;
Andre Przywara5eb4bbe2022-09-11 00:04:41 +0100[diff] [blame]99 regulator-max-microvolt = <1100000>;
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]100 regulator-name = "vdd-cpu";
101 };
102
103 reg_dcdcc: dcdcc {
104 regulator-always-on;
105 regulator-min-microvolt = <810000>;
Andre Przywara5eb4bbe2022-09-11 00:04:41 +0100[diff] [blame]106 regulator-max-microvolt = <990000>;
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]107 regulator-name = "vdd-gpu-sys";
108 };
109
110 reg_dcdcd: dcdcd {
111 regulator-always-on;
112 regulator-min-microvolt = <1500000>;
113 regulator-max-microvolt = <1500000>;
114 regulator-name = "vdd-dram";
115 };
116
117 reg_dcdce: dcdce {
Andre Przywara5eb4bbe2022-09-11 00:04:41 +0100[diff] [blame]118 regulator-always-on;
Jernej Skrabece4e040c2021-01-11 21:11:53 +0100[diff] [blame]119 regulator-min-microvolt = <3300000>;
120 regulator-max-microvolt = <3300000>;
121 regulator-name = "vcc-eth-mmc";
122 };
123
124 sw {
125 /* unused */
126 };
127 };
128 };
129};
130
Andre Przywara5eb4bbe2022-09-11 00:04:41 +0100[diff] [blame]131&pio {
132 vcc-pc-supply = <&reg_aldo1>;
133 vcc-pf-supply = <&reg_aldo1>;
134 vcc-pg-supply = <&reg_bldo1>;
135 vcc-ph-supply = <&reg_aldo1>;
136 vcc-pi-supply = <&reg_aldo1>;
137};