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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard1e1d02d2017-09-13 18:00:12 +02002/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotard1e1d02d2017-09-13 18:00:12 +02005 */
6
7#include <common.h>
8#include <asm/io.h>
Lokesh Vutla076ee452018-04-26 18:21:30 +05309#include <asm/armv7_mpu.h>
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020010
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020011int arch_cpu_init(void)
12{
13 int i;
14
15 struct mpu_region_config stm32_region_config[] = {
16 /*
Patrice Chotard574f4572018-02-28 17:15:00 +010017 * Make SDRAM area cacheable & executable.
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020018 */
Patrice Chotard574f4572018-02-28 17:15:00 +010019#if defined(CONFIG_STM32F4)
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020020 { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
Patrice Chotard574f4572018-02-28 17:15:00 +010021 O_I_WB_RD_WR_ALLOC, REGION_16MB },
22#endif
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020023
Patrice Chotard574f4572018-02-28 17:15:00 +010024#if defined(CONFIG_STM32F7)
25 { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
26 O_I_WB_RD_WR_ALLOC, REGION_16MB },
27#endif
Patrice Chotard0c6247c2017-11-16 08:59:21 +010028
Patrice Chotard574f4572018-02-28 17:15:00 +010029#if defined(CONFIG_STM32H7)
30 { 0xD0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
31 O_I_WB_RD_WR_ALLOC, REGION_32MB },
Patrice Chotard0c6247c2017-11-16 08:59:21 +010032#endif
Patrice Chotard1e1d02d2017-09-13 18:00:12 +020033 };
34
35 disable_mpu();
36 for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
37 mpu_config(&stm32_region_config[i]);
38 enable_mpu();
39
40 return 0;
41}