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Marek Vasut00671d92017-10-09 21:51:10 +02001/*
2 * DHCOM DH-iMX6 PDK board configuration
3 *
4 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __DH_IMX6_CONFIG_H
10#define __DH_IMX6_CONFIG_H
11
12#include <asm/arch/imx-regs.h>
13
14#include <config_distro_defaults.h>
15#include "mx6_common.h"
16
17/*
18 * SPI NOR layout:
19 * 0x00_0000-0x00_ffff ... U-Boot SPL
20 * 0x01_0000-0x0f_ffff ... U-Boot
21 * 0x10_0000-0x10_ffff ... U-Boot env #1
22 * 0x11_0000-0x11_ffff ... U-Boot env #2
23 * 0x12_0000-0x1f_ffff ... UNUSED
24 */
25
26/* SPL */
27#include "imx6_spl.h" /* common IMX6 SPL configuration */
28#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
29#define CONFIG_SPL_SPI_LOAD
30#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
31
32/* Miscellaneous configurable options */
33#define CONFIG_SYS_LONGHELP
34#define CONFIG_AUTO_COMPLETE
35#define CONFIG_CMDLINE_EDITING
36
37#define CONFIG_CMDLINE_TAG
38#define CONFIG_SETUP_MEMORY_TAGS
39#define CONFIG_INITRD_TAG
40#define CONFIG_REVISION_TAG
41
42#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */
43#define CONFIG_BOUNCE_BUFFER
44#define CONFIG_BZIP2
45
46/* Size of malloc() pool */
47#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
48
49/* Bootcounter */
50#define CONFIG_BOOTCOUNT_LIMIT
51#define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR
52#define CONFIG_SYS_BOOTCOUNT_BE
53
54/* FEC ethernet */
55#define CONFIG_MII
56#define IMX_FEC_BASE ENET_BASE_ADDR
57#define CONFIG_FEC_XCV_TYPE RMII
58#define CONFIG_ETHPRIME "FEC"
59#define CONFIG_FEC_MXC_PHYADDR 0
60#define CONFIG_ARP_TIMEOUT 200UL
61
62/* Fuses */
63#ifdef CONFIG_CMD_FUSE
64#define CONFIG_MXC_OCOTP
65#endif
66
67/* GPIO */
68#define CONFIG_MXC_GPIO
69
70/* I2C Configs */
71#define CONFIG_SYS_I2C
72#define CONFIG_SYS_I2C_MXC
73#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
74#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
75#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
76#define CONFIG_SYS_I2C_SPEED 100000
77
78/* MMC Configs */
79#define CONFIG_FSL_ESDHC
80#define CONFIG_FSL_USDHC
81#define CONFIG_SYS_FSL_ESDHC_ADDR 0
82#define CONFIG_SYS_FSL_USDHC_NUM 3
83#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
84
85/* SATA Configs */
86#ifdef CONFIG_CMD_SATA
87#define CONFIG_DWC_AHSATA
88#define CONFIG_SYS_SATA_MAX_DEVICE 1
89#define CONFIG_DWC_AHSATA_PORT_ID 0
90#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
91#define CONFIG_LBA48
92#define CONFIG_LIBATA
93#endif
94
95/* SPI Flash Configs */
96#ifdef CONFIG_CMD_SF
97#define CONFIG_MXC_SPI
98#define CONFIG_SF_DEFAULT_BUS 0
99#define CONFIG_SF_DEFAULT_CS 0
100#define CONFIG_SF_DEFAULT_SPEED 25000000
101#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
102#endif
103
104/* UART */
105#define CONFIG_MXC_UART
106#define CONFIG_MXC_UART_BASE UART1_BASE
107#define CONFIG_CONS_INDEX 1
108#define CONFIG_BAUDRATE 115200
109
110/* USB Configs */
111#ifdef CONFIG_CMD_USB
112#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
113#define CONFIG_USB_HOST_ETHER
114#define CONFIG_USB_ETHER_ASIX
115#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
116#define CONFIG_MXC_USB_FLAGS 0
117#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
Marek Vasut861b6892017-10-22 10:22:40 +0200118
119/* USB Gadget (DFU, UMS) */
120#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
121#define CONFIG_USB_FUNCTION_MASS_STORAGE
122
123#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
124#define DFU_DEFAULT_POLL_TIMEOUT 300
125
126/* USB IDs */
127#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
128#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
129#endif
Marek Vasut00671d92017-10-09 21:51:10 +0200130#endif
131
132/* Watchdog */
133#define CONFIG_HW_WATCHDOG
134#define CONFIG_IMX_WATCHDOG
135#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
136
137/* allow to overwrite serial and ethaddr */
138#define CONFIG_ENV_OVERWRITE
139
140#define CONFIG_SYS_TEXT_BASE 0x17800000
141#define CONFIG_LOADADDR 0x12000000
142#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
143
144#ifndef CONFIG_SPL_BUILD
145#define CONFIG_EXTRA_ENV_SETTINGS \
146 "console=ttymxc0,115200\0" \
147 "fdt_addr=0x18000000\0" \
148 "fdt_high=0xffffffff\0" \
149 "initrd_high=0xffffffff\0" \
150 "kernel_addr_r=0x10008000\0" \
151 "fdt_addr_r=0x13000000\0" \
152 "ramdisk_addr_r=0x18000000\0" \
153 "scriptaddr=0x14000000\0" \
154 "fdtfile=imx6q-dhcom-pdk2.dtb\0"\
155 BOOTENV
156
157#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
158
159#define BOOT_TARGET_DEVICES(func) \
160 func(MMC, mmc, 0) \
161 func(MMC, mmc, 2) \
162 func(USB, usb, 1) \
163 func(SATA, sata, 0) \
164 func(DHCP, dhcp, na)
165
166#include <config_distro_bootcmd.h>
167#endif
168
169/* Physical Memory Map */
170#define CONFIG_NR_DRAM_BANKS 1
171#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
172
173#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
174#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
175#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
176
177#define CONFIG_SYS_INIT_SP_OFFSET \
178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
179
180#define CONFIG_SYS_INIT_SP_ADDR \
181 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
182
183#define CONFIG_SYS_MEMTEST_START 0x10000000
184#define CONFIG_SYS_MEMTEST_END 0x20000000
185#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
186
187/* Environment */
188#define CONFIG_ENV_SIZE (16 * 1024)
189#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
190
191#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
192#define CONFIG_ENV_OFFSET (1024 * 1024)
193#define CONFIG_ENV_SECT_SIZE (64 * 1024)
194#define CONFIG_ENV_OFFSET_REDUND \
195 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
196#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
197#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
198#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
199#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
200#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
201#endif
202
203#endif /* __DH_IMX6_CONFIG_H */