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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +03002/*
3 * include/configs/porter.h
4 * This file is Porter board configuration.
5 *
6 * Copyright (C) 2015 Renesas Electronics Corporation
7 * Copyright (C) 2015 Cogent Embedded, Inc.
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +03008 */
9
10#ifndef __PORTER_H
11#define __PORTER_H
12
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030013#include "rcar-gen2-common.h"
14
Marek Vasut10469062018-02-16 01:33:27 +010015#define STACK_AREA_SIZE 0x00100000
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030016#define LOW_LEVEL_MERAM_STACK \
Tom Rini4ddbade2022-05-25 12:16:03 -040017 (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030018
19/* MEMORY */
20#define RCAR_GEN2_SDRAM_BASE 0x40000000
21#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
22#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
23
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030024/* SH Ether */
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030025#define CONFIG_SH_ETHER_USE_PORT 0
26#define CONFIG_SH_ETHER_PHY_ADDR 0x1
27#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
Tom Rini872054f2022-12-04 10:13:49 -050028#define CFG_SH_ETHER_CACHE_WRITEBACK
Tom Rinia44cb162022-12-04 10:13:48 -050029#define CFG_SH_ETHER_CACHE_INVALIDATE
Tom Rinidd2eba02022-12-04 10:13:47 -050030#define CFG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030031
32/* Board Clock */
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030033
Tom Rinic9edebe2022-12-04 10:03:50 -050034#define CFG_EXTRA_ENV_SETTINGS \
Marek Vasut4f34a4b2018-11-27 00:19:03 +010035 "bootm_size=0x10000000\0"
Marek Vasute7206be2018-02-17 01:21:15 +010036
Marek Vasut10469062018-02-16 01:33:27 +010037/* SPL support */
Marek Vasutc80de6c2018-04-03 12:52:48 +020038
Vladimir Barinov2f8c00e2015-02-14 01:06:13 +030039#endif /* __PORTER_H */