blob: 63f2086dece4a726f72abb830c9bab06cdb8f2d6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warren50709602016-10-21 14:46:47 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 *
Stephen Warren50709602016-10-21 14:46:47 -06005 * Portions based on U-Boot's rtl8169.c.
6 */
7
8/*
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
12 *
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
20 * field.
21 *
22 * The following configurations are currently supported:
23 * tegra186:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
28 */
Stephen Warren50709602016-10-21 14:46:47 -060029#include <common.h>
30#include <clk.h>
Simon Glass63334482019-11-14 12:57:39 -070031#include <cpu_func.h>
Stephen Warren50709602016-10-21 14:46:47 -060032#include <dm.h>
33#include <errno.h>
Simon Glass9bc15642020-02-03 07:36:16 -070034#include <malloc.h>
Stephen Warren50709602016-10-21 14:46:47 -060035#include <memalign.h>
36#include <miiphy.h>
37#include <net.h>
38#include <netdev.h>
39#include <phy.h>
40#include <reset.h>
41#include <wait_bit.h>
42#include <asm/gpio.h>
43#include <asm/io.h>
44
45/* Core registers */
46
47#define EQOS_MAC_REGS_BASE 0x000
48struct eqos_mac_regs {
49 uint32_t configuration; /* 0x000 */
50 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
51 uint32_t q0_tx_flow_ctrl; /* 0x070 */
52 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
53 uint32_t rx_flow_ctrl; /* 0x090 */
54 uint32_t unused_094; /* 0x094 */
55 uint32_t txq_prty_map0; /* 0x098 */
56 uint32_t unused_09c; /* 0x09c */
57 uint32_t rxq_ctrl0; /* 0x0a0 */
58 uint32_t unused_0a4; /* 0x0a4 */
59 uint32_t rxq_ctrl2; /* 0x0a8 */
60 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
61 uint32_t us_tic_counter; /* 0x0dc */
62 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
63 uint32_t hw_feature0; /* 0x11c */
64 uint32_t hw_feature1; /* 0x120 */
65 uint32_t hw_feature2; /* 0x124 */
66 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
67 uint32_t mdio_address; /* 0x200 */
68 uint32_t mdio_data; /* 0x204 */
69 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
70 uint32_t address0_high; /* 0x300 */
71 uint32_t address0_low; /* 0x304 */
72};
73
74#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
75#define EQOS_MAC_CONFIGURATION_CST BIT(21)
76#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
77#define EQOS_MAC_CONFIGURATION_WD BIT(19)
78#define EQOS_MAC_CONFIGURATION_JD BIT(17)
79#define EQOS_MAC_CONFIGURATION_JE BIT(16)
80#define EQOS_MAC_CONFIGURATION_PS BIT(15)
81#define EQOS_MAC_CONFIGURATION_FES BIT(14)
82#define EQOS_MAC_CONFIGURATION_DM BIT(13)
83#define EQOS_MAC_CONFIGURATION_TE BIT(1)
84#define EQOS_MAC_CONFIGURATION_RE BIT(0)
85
86#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
87#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
88#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
89
90#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
91
92#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
93#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
94
95#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
96#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
97#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
98#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
Christophe Roullier6beb7802019-05-17 15:08:44 +020099#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
Stephen Warren50709602016-10-21 14:46:47 -0600100
101#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
102#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
103
104#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
105#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
106#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
107#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
108
109#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
110#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
111#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
112#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
Christophe Roullier6beb7802019-05-17 15:08:44 +0200113#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
Stephen Warren50709602016-10-21 14:46:47 -0600114#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
115#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
116#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
117#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
118#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
119#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
120
121#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
122
123#define EQOS_MTL_REGS_BASE 0xd00
124struct eqos_mtl_regs {
125 uint32_t txq0_operation_mode; /* 0xd00 */
126 uint32_t unused_d04; /* 0xd04 */
127 uint32_t txq0_debug; /* 0xd08 */
128 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
129 uint32_t txq0_quantum_weight; /* 0xd18 */
130 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
131 uint32_t rxq0_operation_mode; /* 0xd30 */
132 uint32_t unused_d34; /* 0xd34 */
133 uint32_t rxq0_debug; /* 0xd38 */
134};
135
136#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
137#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
138#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
139#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
140#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
141#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
142#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
143
144#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
145#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
146#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
147
148#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
149#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
150#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
151#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
152#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
153#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
154#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
155#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
156
157#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
158#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
159#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
160#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
161
162#define EQOS_DMA_REGS_BASE 0x1000
163struct eqos_dma_regs {
164 uint32_t mode; /* 0x1000 */
165 uint32_t sysbus_mode; /* 0x1004 */
166 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
167 uint32_t ch0_control; /* 0x1100 */
168 uint32_t ch0_tx_control; /* 0x1104 */
169 uint32_t ch0_rx_control; /* 0x1108 */
170 uint32_t unused_110c; /* 0x110c */
171 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
172 uint32_t ch0_txdesc_list_address; /* 0x1114 */
173 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
174 uint32_t ch0_rxdesc_list_address; /* 0x111c */
175 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
176 uint32_t unused_1124; /* 0x1124 */
177 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
178 uint32_t ch0_txdesc_ring_length; /* 0x112c */
179 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
180};
181
182#define EQOS_DMA_MODE_SWR BIT(0)
183
184#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
185#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
186#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
187#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
188#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
189#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
190
191#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
192
193#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
194#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
195#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
196#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
197
198#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
199#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
200#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
201#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
202#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
203
204/* These registers are Tegra186-specific */
205#define EQOS_TEGRA186_REGS_BASE 0x8800
206struct eqos_tegra186_regs {
207 uint32_t sdmemcomppadctrl; /* 0x8800 */
208 uint32_t auto_cal_config; /* 0x8804 */
209 uint32_t unused_8808; /* 0x8808 */
210 uint32_t auto_cal_status; /* 0x880c */
211};
212
213#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
214
215#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
216#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
217
218#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
219
220/* Descriptors */
221
222#define EQOS_DESCRIPTOR_WORDS 4
223#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
224/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
225#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
226#define EQOS_DESCRIPTORS_TX 4
227#define EQOS_DESCRIPTORS_RX 4
228#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
229#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
230 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
231#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
232#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
233#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
234
235/*
236 * Warn if the cache-line size is larger than the descriptor size. In such
237 * cases the driver will likely fail because the CPU needs to flush the cache
238 * when requeuing RX buffers, therefore descriptors written by the hardware
239 * may be discarded. Architectures with full IO coherence, such as x86, do not
240 * experience this issue, and hence are excluded from this condition.
241 *
242 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
243 * the driver to allocate descriptors from a pool of non-cached memory.
244 */
245#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
246#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400247 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
Stephen Warren50709602016-10-21 14:46:47 -0600248#warning Cache line size is larger than descriptor size
249#endif
250#endif
251
252struct eqos_desc {
253 u32 des0;
254 u32 des1;
255 u32 des2;
256 u32 des3;
257};
258
259#define EQOS_DESC3_OWN BIT(31)
260#define EQOS_DESC3_FD BIT(29)
261#define EQOS_DESC3_LD BIT(28)
262#define EQOS_DESC3_BUF1V BIT(24)
263
264struct eqos_config {
265 bool reg_access_always_ok;
Christophe Roullier6beb7802019-05-17 15:08:44 +0200266 int mdio_wait;
267 int swr_wait;
268 int config_mac;
269 int config_mac_mdio;
270 phy_interface_t (*interface)(struct udevice *dev);
271 struct eqos_ops *ops;
272};
273
274struct eqos_ops {
275 void (*eqos_inval_desc)(void *desc);
276 void (*eqos_flush_desc)(void *desc);
277 void (*eqos_inval_buffer)(void *buf, size_t size);
278 void (*eqos_flush_buffer)(void *buf, size_t size);
279 int (*eqos_probe_resources)(struct udevice *dev);
280 int (*eqos_remove_resources)(struct udevice *dev);
281 int (*eqos_stop_resets)(struct udevice *dev);
282 int (*eqos_start_resets)(struct udevice *dev);
283 void (*eqos_stop_clks)(struct udevice *dev);
284 int (*eqos_start_clks)(struct udevice *dev);
285 int (*eqos_calibrate_pads)(struct udevice *dev);
286 int (*eqos_disable_calibration)(struct udevice *dev);
287 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
288 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
Stephen Warren50709602016-10-21 14:46:47 -0600289};
290
291struct eqos_priv {
292 struct udevice *dev;
293 const struct eqos_config *config;
294 fdt_addr_t regs;
295 struct eqos_mac_regs *mac_regs;
296 struct eqos_mtl_regs *mtl_regs;
297 struct eqos_dma_regs *dma_regs;
298 struct eqos_tegra186_regs *tegra186_regs;
299 struct reset_ctl reset_ctl;
300 struct gpio_desc phy_reset_gpio;
301 struct clk clk_master_bus;
302 struct clk clk_rx;
303 struct clk clk_ptp_ref;
304 struct clk clk_tx;
Christophe Roullier6beb7802019-05-17 15:08:44 +0200305 struct clk clk_ck;
Stephen Warren50709602016-10-21 14:46:47 -0600306 struct clk clk_slave_bus;
307 struct mii_dev *mii;
308 struct phy_device *phy;
Patrick Delaunay5c8db372020-03-18 10:50:16 +0100309 int phyaddr;
310 u32 max_speed;
Stephen Warren50709602016-10-21 14:46:47 -0600311 void *descs;
312 struct eqos_desc *tx_descs;
313 struct eqos_desc *rx_descs;
314 int tx_desc_idx, rx_desc_idx;
315 void *tx_dma_buf;
316 void *rx_dma_buf;
317 void *rx_pkt;
318 bool started;
319 bool reg_access_ok;
320};
321
322/*
323 * TX and RX descriptors are 16 bytes. This causes problems with the cache
324 * maintenance on CPUs where the cache-line size exceeds the size of these
325 * descriptors. What will happen is that when the driver receives a packet
326 * it will be immediately requeued for the hardware to reuse. The CPU will
327 * therefore need to flush the cache-line containing the descriptor, which
328 * will cause all other descriptors in the same cache-line to be flushed
329 * along with it. If one of those descriptors had been written to by the
330 * device those changes (and the associated packet) will be lost.
331 *
332 * To work around this, we make use of non-cached memory if available. If
333 * descriptors are mapped uncached there's no need to manually flush them
334 * or invalidate them.
335 *
336 * Note that this only applies to descriptors. The packet data buffers do
337 * not have the same constraints since they are 1536 bytes large, so they
338 * are unlikely to share cache-lines.
339 */
340static void *eqos_alloc_descs(unsigned int num)
341{
342#ifdef CONFIG_SYS_NONCACHED_MEMORY
343 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
344 EQOS_DESCRIPTOR_ALIGN);
345#else
346 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
347#endif
348}
349
350static void eqos_free_descs(void *descs)
351{
352#ifdef CONFIG_SYS_NONCACHED_MEMORY
353 /* FIXME: noncached_alloc() has no opposite */
354#else
355 free(descs);
356#endif
357}
358
Christophe Roullier6beb7802019-05-17 15:08:44 +0200359static void eqos_inval_desc_tegra186(void *desc)
Stephen Warren50709602016-10-21 14:46:47 -0600360{
361#ifndef CONFIG_SYS_NONCACHED_MEMORY
362 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
363 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
364 ARCH_DMA_MINALIGN);
365
366 invalidate_dcache_range(start, end);
367#endif
368}
369
Christophe Roullier6beb7802019-05-17 15:08:44 +0200370static void eqos_inval_desc_stm32(void *desc)
Stephen Warren50709602016-10-21 14:46:47 -0600371{
372#ifndef CONFIG_SYS_NONCACHED_MEMORY
Christophe Roullier6beb7802019-05-17 15:08:44 +0200373 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
374 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
375 ARCH_DMA_MINALIGN);
376
377 invalidate_dcache_range(start, end);
378#endif
379}
380
381static void eqos_flush_desc_tegra186(void *desc)
382{
383#ifndef CONFIG_SYS_NONCACHED_MEMORY
Stephen Warren50709602016-10-21 14:46:47 -0600384 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
385#endif
386}
387
Christophe Roullier6beb7802019-05-17 15:08:44 +0200388static void eqos_flush_desc_stm32(void *desc)
389{
390#ifndef CONFIG_SYS_NONCACHED_MEMORY
391 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
392 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
393 ARCH_DMA_MINALIGN);
394
395 flush_dcache_range(start, end);
396#endif
397}
398
399static void eqos_inval_buffer_tegra186(void *buf, size_t size)
Stephen Warren50709602016-10-21 14:46:47 -0600400{
401 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
402 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
403
404 invalidate_dcache_range(start, end);
405}
406
Christophe Roullier6beb7802019-05-17 15:08:44 +0200407static void eqos_inval_buffer_stm32(void *buf, size_t size)
408{
409 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
410 unsigned long end = roundup((unsigned long)buf + size,
411 ARCH_DMA_MINALIGN);
412
413 invalidate_dcache_range(start, end);
414}
415
416static void eqos_flush_buffer_tegra186(void *buf, size_t size)
Stephen Warren50709602016-10-21 14:46:47 -0600417{
418 flush_cache((unsigned long)buf, size);
419}
420
Christophe Roullier6beb7802019-05-17 15:08:44 +0200421static void eqos_flush_buffer_stm32(void *buf, size_t size)
422{
423 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
424 unsigned long end = roundup((unsigned long)buf + size,
425 ARCH_DMA_MINALIGN);
426
427 flush_dcache_range(start, end);
428}
429
Stephen Warren50709602016-10-21 14:46:47 -0600430static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
431{
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100432 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
433 EQOS_MAC_MDIO_ADDRESS_GB, false,
434 1000000, true);
Stephen Warren50709602016-10-21 14:46:47 -0600435}
436
437static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
438 int mdio_reg)
439{
440 struct eqos_priv *eqos = bus->priv;
441 u32 val;
442 int ret;
443
444 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
445 mdio_reg);
446
447 ret = eqos_mdio_wait_idle(eqos);
448 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900449 pr_err("MDIO not idle at entry");
Stephen Warren50709602016-10-21 14:46:47 -0600450 return ret;
451 }
452
453 val = readl(&eqos->mac_regs->mdio_address);
454 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
455 EQOS_MAC_MDIO_ADDRESS_C45E;
456 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
457 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullier6beb7802019-05-17 15:08:44 +0200458 (eqos->config->config_mac_mdio <<
Stephen Warren50709602016-10-21 14:46:47 -0600459 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
460 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
461 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
462 EQOS_MAC_MDIO_ADDRESS_GB;
463 writel(val, &eqos->mac_regs->mdio_address);
464
Christophe Roullier6beb7802019-05-17 15:08:44 +0200465 udelay(eqos->config->mdio_wait);
Stephen Warren50709602016-10-21 14:46:47 -0600466
467 ret = eqos_mdio_wait_idle(eqos);
468 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900469 pr_err("MDIO read didn't complete");
Stephen Warren50709602016-10-21 14:46:47 -0600470 return ret;
471 }
472
473 val = readl(&eqos->mac_regs->mdio_data);
474 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
475
476 debug("%s: val=%x\n", __func__, val);
477
478 return val;
479}
480
481static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
482 int mdio_reg, u16 mdio_val)
483{
484 struct eqos_priv *eqos = bus->priv;
485 u32 val;
486 int ret;
487
488 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
489 mdio_addr, mdio_reg, mdio_val);
490
491 ret = eqos_mdio_wait_idle(eqos);
492 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900493 pr_err("MDIO not idle at entry");
Stephen Warren50709602016-10-21 14:46:47 -0600494 return ret;
495 }
496
497 writel(mdio_val, &eqos->mac_regs->mdio_data);
498
499 val = readl(&eqos->mac_regs->mdio_address);
500 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
501 EQOS_MAC_MDIO_ADDRESS_C45E;
502 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
503 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullier6beb7802019-05-17 15:08:44 +0200504 (eqos->config->config_mac_mdio <<
Stephen Warren50709602016-10-21 14:46:47 -0600505 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
506 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
507 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
508 EQOS_MAC_MDIO_ADDRESS_GB;
509 writel(val, &eqos->mac_regs->mdio_address);
510
Christophe Roullier6beb7802019-05-17 15:08:44 +0200511 udelay(eqos->config->mdio_wait);
Stephen Warren50709602016-10-21 14:46:47 -0600512
513 ret = eqos_mdio_wait_idle(eqos);
514 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900515 pr_err("MDIO read didn't complete");
Stephen Warren50709602016-10-21 14:46:47 -0600516 return ret;
517 }
518
519 return 0;
520}
521
522static int eqos_start_clks_tegra186(struct udevice *dev)
523{
524 struct eqos_priv *eqos = dev_get_priv(dev);
525 int ret;
526
527 debug("%s(dev=%p):\n", __func__, dev);
528
529 ret = clk_enable(&eqos->clk_slave_bus);
530 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900531 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600532 goto err;
533 }
534
535 ret = clk_enable(&eqos->clk_master_bus);
536 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900537 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600538 goto err_disable_clk_slave_bus;
539 }
540
541 ret = clk_enable(&eqos->clk_rx);
542 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900543 pr_err("clk_enable(clk_rx) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600544 goto err_disable_clk_master_bus;
545 }
546
547 ret = clk_enable(&eqos->clk_ptp_ref);
548 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900549 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600550 goto err_disable_clk_rx;
551 }
552
553 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
554 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900555 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600556 goto err_disable_clk_ptp_ref;
557 }
558
559 ret = clk_enable(&eqos->clk_tx);
560 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900561 pr_err("clk_enable(clk_tx) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600562 goto err_disable_clk_ptp_ref;
563 }
564
565 debug("%s: OK\n", __func__);
566 return 0;
567
568err_disable_clk_ptp_ref:
569 clk_disable(&eqos->clk_ptp_ref);
570err_disable_clk_rx:
571 clk_disable(&eqos->clk_rx);
572err_disable_clk_master_bus:
573 clk_disable(&eqos->clk_master_bus);
574err_disable_clk_slave_bus:
575 clk_disable(&eqos->clk_slave_bus);
576err:
577 debug("%s: FAILED: %d\n", __func__, ret);
578 return ret;
579}
580
Christophe Roullier6beb7802019-05-17 15:08:44 +0200581static int eqos_start_clks_stm32(struct udevice *dev)
582{
583 struct eqos_priv *eqos = dev_get_priv(dev);
584 int ret;
585
586 debug("%s(dev=%p):\n", __func__, dev);
587
588 ret = clk_enable(&eqos->clk_master_bus);
589 if (ret < 0) {
590 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
591 goto err;
592 }
593
594 ret = clk_enable(&eqos->clk_rx);
595 if (ret < 0) {
596 pr_err("clk_enable(clk_rx) failed: %d", ret);
597 goto err_disable_clk_master_bus;
598 }
599
600 ret = clk_enable(&eqos->clk_tx);
601 if (ret < 0) {
602 pr_err("clk_enable(clk_tx) failed: %d", ret);
603 goto err_disable_clk_rx;
604 }
605
606 if (clk_valid(&eqos->clk_ck)) {
607 ret = clk_enable(&eqos->clk_ck);
608 if (ret < 0) {
609 pr_err("clk_enable(clk_ck) failed: %d", ret);
610 goto err_disable_clk_tx;
611 }
612 }
613
614 debug("%s: OK\n", __func__);
615 return 0;
616
617err_disable_clk_tx:
618 clk_disable(&eqos->clk_tx);
619err_disable_clk_rx:
620 clk_disable(&eqos->clk_rx);
621err_disable_clk_master_bus:
622 clk_disable(&eqos->clk_master_bus);
623err:
624 debug("%s: FAILED: %d\n", __func__, ret);
625 return ret;
626}
627
Patrick Delaunay6864a5992019-08-01 11:29:02 +0200628static void eqos_stop_clks_tegra186(struct udevice *dev)
Stephen Warren50709602016-10-21 14:46:47 -0600629{
630 struct eqos_priv *eqos = dev_get_priv(dev);
631
632 debug("%s(dev=%p):\n", __func__, dev);
633
634 clk_disable(&eqos->clk_tx);
635 clk_disable(&eqos->clk_ptp_ref);
636 clk_disable(&eqos->clk_rx);
637 clk_disable(&eqos->clk_master_bus);
638 clk_disable(&eqos->clk_slave_bus);
639
640 debug("%s: OK\n", __func__);
641}
642
Patrick Delaunay6864a5992019-08-01 11:29:02 +0200643static void eqos_stop_clks_stm32(struct udevice *dev)
Christophe Roullier6beb7802019-05-17 15:08:44 +0200644{
645 struct eqos_priv *eqos = dev_get_priv(dev);
646
647 debug("%s(dev=%p):\n", __func__, dev);
648
649 clk_disable(&eqos->clk_tx);
650 clk_disable(&eqos->clk_rx);
651 clk_disable(&eqos->clk_master_bus);
652 if (clk_valid(&eqos->clk_ck))
653 clk_disable(&eqos->clk_ck);
654
655 debug("%s: OK\n", __func__);
656}
657
Stephen Warren50709602016-10-21 14:46:47 -0600658static int eqos_start_resets_tegra186(struct udevice *dev)
659{
660 struct eqos_priv *eqos = dev_get_priv(dev);
661 int ret;
662
663 debug("%s(dev=%p):\n", __func__, dev);
664
665 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
666 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900667 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600668 return ret;
669 }
670
671 udelay(2);
672
673 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
674 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900675 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600676 return ret;
677 }
678
679 ret = reset_assert(&eqos->reset_ctl);
680 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900681 pr_err("reset_assert() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600682 return ret;
683 }
684
685 udelay(2);
686
687 ret = reset_deassert(&eqos->reset_ctl);
688 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900689 pr_err("reset_deassert() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600690 return ret;
691 }
692
693 debug("%s: OK\n", __func__);
694 return 0;
695}
696
Christophe Roullier6beb7802019-05-17 15:08:44 +0200697static int eqos_start_resets_stm32(struct udevice *dev)
698{
Christophe Roullier104dab52020-03-18 10:50:15 +0100699 struct eqos_priv *eqos = dev_get_priv(dev);
700 int ret;
701
702 debug("%s(dev=%p):\n", __func__, dev);
703 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
704 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
705 if (ret < 0) {
706 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
707 ret);
708 return ret;
709 }
710
711 udelay(2);
712
713 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
714 if (ret < 0) {
715 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
716 ret);
717 return ret;
718 }
719 }
720 debug("%s: OK\n", __func__);
721
Christophe Roullier6beb7802019-05-17 15:08:44 +0200722 return 0;
723}
724
Stephen Warren50709602016-10-21 14:46:47 -0600725static int eqos_stop_resets_tegra186(struct udevice *dev)
726{
727 struct eqos_priv *eqos = dev_get_priv(dev);
728
729 reset_assert(&eqos->reset_ctl);
730 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
731
Christophe Roullier6beb7802019-05-17 15:08:44 +0200732 return 0;
733}
734
735static int eqos_stop_resets_stm32(struct udevice *dev)
736{
Christophe Roullier104dab52020-03-18 10:50:15 +0100737 struct eqos_priv *eqos = dev_get_priv(dev);
738 int ret;
739
740 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
741 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
742 if (ret < 0) {
743 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
744 ret);
745 return ret;
746 }
747 }
748
Stephen Warren50709602016-10-21 14:46:47 -0600749 return 0;
750}
751
752static int eqos_calibrate_pads_tegra186(struct udevice *dev)
753{
754 struct eqos_priv *eqos = dev_get_priv(dev);
755 int ret;
756
757 debug("%s(dev=%p):\n", __func__, dev);
758
759 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
760 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
761
762 udelay(1);
763
764 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
765 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
766
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100767 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
768 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
Stephen Warren50709602016-10-21 14:46:47 -0600769 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900770 pr_err("calibrate didn't start");
Stephen Warren50709602016-10-21 14:46:47 -0600771 goto failed;
772 }
773
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100774 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
775 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
Stephen Warren50709602016-10-21 14:46:47 -0600776 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900777 pr_err("calibrate didn't finish");
Stephen Warren50709602016-10-21 14:46:47 -0600778 goto failed;
779 }
780
781 ret = 0;
782
783failed:
784 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
785 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
786
787 debug("%s: returns %d\n", __func__, ret);
788
789 return ret;
790}
791
792static int eqos_disable_calibration_tegra186(struct udevice *dev)
793{
794 struct eqos_priv *eqos = dev_get_priv(dev);
795
796 debug("%s(dev=%p):\n", __func__, dev);
797
798 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
799 EQOS_AUTO_CAL_CONFIG_ENABLE);
800
801 return 0;
802}
803
804static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
805{
806 struct eqos_priv *eqos = dev_get_priv(dev);
807
808 return clk_get_rate(&eqos->clk_slave_bus);
809}
810
Christophe Roullier6beb7802019-05-17 15:08:44 +0200811static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
812{
813 struct eqos_priv *eqos = dev_get_priv(dev);
814
815 return clk_get_rate(&eqos->clk_master_bus);
816}
817
818static int eqos_calibrate_pads_stm32(struct udevice *dev)
819{
820 return 0;
821}
822
823static int eqos_disable_calibration_stm32(struct udevice *dev)
824{
825 return 0;
826}
827
Stephen Warren50709602016-10-21 14:46:47 -0600828static int eqos_set_full_duplex(struct udevice *dev)
829{
830 struct eqos_priv *eqos = dev_get_priv(dev);
831
832 debug("%s(dev=%p):\n", __func__, dev);
833
834 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
835
836 return 0;
837}
838
839static int eqos_set_half_duplex(struct udevice *dev)
840{
841 struct eqos_priv *eqos = dev_get_priv(dev);
842
843 debug("%s(dev=%p):\n", __func__, dev);
844
845 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
846
847 /* WAR: Flush TX queue when switching to half-duplex */
848 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
849 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
850
851 return 0;
852}
853
854static int eqos_set_gmii_speed(struct udevice *dev)
855{
856 struct eqos_priv *eqos = dev_get_priv(dev);
857
858 debug("%s(dev=%p):\n", __func__, dev);
859
860 clrbits_le32(&eqos->mac_regs->configuration,
861 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
862
863 return 0;
864}
865
866static int eqos_set_mii_speed_100(struct udevice *dev)
867{
868 struct eqos_priv *eqos = dev_get_priv(dev);
869
870 debug("%s(dev=%p):\n", __func__, dev);
871
872 setbits_le32(&eqos->mac_regs->configuration,
873 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
874
875 return 0;
876}
877
878static int eqos_set_mii_speed_10(struct udevice *dev)
879{
880 struct eqos_priv *eqos = dev_get_priv(dev);
881
882 debug("%s(dev=%p):\n", __func__, dev);
883
884 clrsetbits_le32(&eqos->mac_regs->configuration,
885 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
886
887 return 0;
888}
889
890static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
891{
892 struct eqos_priv *eqos = dev_get_priv(dev);
893 ulong rate;
894 int ret;
895
896 debug("%s(dev=%p):\n", __func__, dev);
897
898 switch (eqos->phy->speed) {
899 case SPEED_1000:
900 rate = 125 * 1000 * 1000;
901 break;
902 case SPEED_100:
903 rate = 25 * 1000 * 1000;
904 break;
905 case SPEED_10:
906 rate = 2.5 * 1000 * 1000;
907 break;
908 default:
Masahiro Yamada81e10422017-09-16 14:10:41 +0900909 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warren50709602016-10-21 14:46:47 -0600910 return -EINVAL;
911 }
912
913 ret = clk_set_rate(&eqos->clk_tx, rate);
914 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900915 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
Stephen Warren50709602016-10-21 14:46:47 -0600916 return ret;
917 }
918
919 return 0;
920}
921
Christophe Roullier6beb7802019-05-17 15:08:44 +0200922static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
923{
924 return 0;
925}
926
Stephen Warren50709602016-10-21 14:46:47 -0600927static int eqos_adjust_link(struct udevice *dev)
928{
929 struct eqos_priv *eqos = dev_get_priv(dev);
930 int ret;
931 bool en_calibration;
932
933 debug("%s(dev=%p):\n", __func__, dev);
934
935 if (eqos->phy->duplex)
936 ret = eqos_set_full_duplex(dev);
937 else
938 ret = eqos_set_half_duplex(dev);
939 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900940 pr_err("eqos_set_*_duplex() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600941 return ret;
942 }
943
944 switch (eqos->phy->speed) {
945 case SPEED_1000:
946 en_calibration = true;
947 ret = eqos_set_gmii_speed(dev);
948 break;
949 case SPEED_100:
950 en_calibration = true;
951 ret = eqos_set_mii_speed_100(dev);
952 break;
953 case SPEED_10:
954 en_calibration = false;
955 ret = eqos_set_mii_speed_10(dev);
956 break;
957 default:
Masahiro Yamada81e10422017-09-16 14:10:41 +0900958 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warren50709602016-10-21 14:46:47 -0600959 return -EINVAL;
960 }
961 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900962 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600963 return ret;
964 }
965
966 if (en_calibration) {
Christophe Roullier6beb7802019-05-17 15:08:44 +0200967 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warren50709602016-10-21 14:46:47 -0600968 if (ret < 0) {
Christophe Roullier6beb7802019-05-17 15:08:44 +0200969 pr_err("eqos_calibrate_pads() failed: %d",
970 ret);
Stephen Warren50709602016-10-21 14:46:47 -0600971 return ret;
972 }
973 } else {
Christophe Roullier6beb7802019-05-17 15:08:44 +0200974 ret = eqos->config->ops->eqos_disable_calibration(dev);
Stephen Warren50709602016-10-21 14:46:47 -0600975 if (ret < 0) {
Christophe Roullier6beb7802019-05-17 15:08:44 +0200976 pr_err("eqos_disable_calibration() failed: %d",
977 ret);
Stephen Warren50709602016-10-21 14:46:47 -0600978 return ret;
979 }
980 }
Christophe Roullier6beb7802019-05-17 15:08:44 +0200981 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
Stephen Warren50709602016-10-21 14:46:47 -0600982 if (ret < 0) {
Christophe Roullier6beb7802019-05-17 15:08:44 +0200983 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -0600984 return ret;
985 }
986
987 return 0;
988}
989
990static int eqos_write_hwaddr(struct udevice *dev)
991{
992 struct eth_pdata *plat = dev_get_platdata(dev);
993 struct eqos_priv *eqos = dev_get_priv(dev);
994 uint32_t val;
995
996 /*
997 * This function may be called before start() or after stop(). At that
998 * time, on at least some configurations of the EQoS HW, all clocks to
999 * the EQoS HW block will be stopped, and a reset signal applied. If
1000 * any register access is attempted in this state, bus timeouts or CPU
1001 * hangs may occur. This check prevents that.
1002 *
1003 * A simple solution to this problem would be to not implement
1004 * write_hwaddr(), since start() always writes the MAC address into HW
1005 * anyway. However, it is desirable to implement write_hwaddr() to
1006 * support the case of SW that runs subsequent to U-Boot which expects
1007 * the MAC address to already be programmed into the EQoS registers,
1008 * which must happen irrespective of whether the U-Boot user (or
1009 * scripts) actually made use of the EQoS device, and hence
1010 * irrespective of whether start() was ever called.
1011 *
1012 * Note that this requirement by subsequent SW is not valid for
1013 * Tegra186, and is likely not valid for any non-PCI instantiation of
1014 * the EQoS HW block. This function is implemented solely as
1015 * future-proofing with the expectation the driver will eventually be
1016 * ported to some system where the expectation above is true.
1017 */
1018 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
1019 return 0;
1020
1021 /* Update the MAC address */
1022 val = (plat->enetaddr[5] << 8) |
1023 (plat->enetaddr[4]);
1024 writel(val, &eqos->mac_regs->address0_high);
1025 val = (plat->enetaddr[3] << 24) |
1026 (plat->enetaddr[2] << 16) |
1027 (plat->enetaddr[1] << 8) |
1028 (plat->enetaddr[0]);
1029 writel(val, &eqos->mac_regs->address0_low);
1030
1031 return 0;
1032}
1033
1034static int eqos_start(struct udevice *dev)
1035{
1036 struct eqos_priv *eqos = dev_get_priv(dev);
1037 int ret, i;
1038 ulong rate;
1039 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1040 ulong last_rx_desc;
1041
1042 debug("%s(dev=%p):\n", __func__, dev);
1043
1044 eqos->tx_desc_idx = 0;
1045 eqos->rx_desc_idx = 0;
1046
Christophe Roullier6beb7802019-05-17 15:08:44 +02001047 ret = eqos->config->ops->eqos_start_clks(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001048 if (ret < 0) {
Christophe Roullier6beb7802019-05-17 15:08:44 +02001049 pr_err("eqos_start_clks() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001050 goto err;
1051 }
1052
Christophe Roullier6beb7802019-05-17 15:08:44 +02001053 ret = eqos->config->ops->eqos_start_resets(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001054 if (ret < 0) {
Christophe Roullier6beb7802019-05-17 15:08:44 +02001055 pr_err("eqos_start_resets() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001056 goto err_stop_clks;
1057 }
1058
1059 udelay(10);
1060
1061 eqos->reg_access_ok = true;
1062
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +01001063 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
Christophe Roullier6beb7802019-05-17 15:08:44 +02001064 EQOS_DMA_MODE_SWR, false,
1065 eqos->config->swr_wait, false);
Stephen Warren50709602016-10-21 14:46:47 -06001066 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001067 pr_err("EQOS_DMA_MODE_SWR stuck");
Stephen Warren50709602016-10-21 14:46:47 -06001068 goto err_stop_resets;
1069 }
1070
Christophe Roullier6beb7802019-05-17 15:08:44 +02001071 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001072 if (ret < 0) {
Christophe Roullier6beb7802019-05-17 15:08:44 +02001073 pr_err("eqos_calibrate_pads() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001074 goto err_stop_resets;
1075 }
Christophe Roullier6beb7802019-05-17 15:08:44 +02001076 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001077
Stephen Warren50709602016-10-21 14:46:47 -06001078 val = (rate / 1000000) - 1;
1079 writel(val, &eqos->mac_regs->us_tic_counter);
1080
Christophe Roullier6beb7802019-05-17 15:08:44 +02001081 /*
1082 * if PHY was already connected and configured,
1083 * don't need to reconnect/reconfigure again
1084 */
Stephen Warren50709602016-10-21 14:46:47 -06001085 if (!eqos->phy) {
Patrick Delaunay5c8db372020-03-18 10:50:16 +01001086 eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev,
Christophe Roullier6beb7802019-05-17 15:08:44 +02001087 eqos->config->interface(dev));
1088 if (!eqos->phy) {
1089 pr_err("phy_connect() failed");
1090 goto err_stop_resets;
1091 }
Patrick Delaunay5c8db372020-03-18 10:50:16 +01001092
1093 if (eqos->max_speed) {
1094 ret = phy_set_supported(eqos->phy, eqos->max_speed);
1095 if (ret) {
1096 pr_err("phy_set_supported() failed: %d", ret);
1097 goto err_shutdown_phy;
1098 }
1099 }
1100
Christophe Roullier6beb7802019-05-17 15:08:44 +02001101 ret = phy_config(eqos->phy);
1102 if (ret < 0) {
1103 pr_err("phy_config() failed: %d", ret);
1104 goto err_shutdown_phy;
1105 }
Stephen Warren50709602016-10-21 14:46:47 -06001106 }
Christophe Roullier6beb7802019-05-17 15:08:44 +02001107
Stephen Warren50709602016-10-21 14:46:47 -06001108 ret = phy_startup(eqos->phy);
1109 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001110 pr_err("phy_startup() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001111 goto err_shutdown_phy;
1112 }
1113
1114 if (!eqos->phy->link) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001115 pr_err("No link");
Stephen Warren50709602016-10-21 14:46:47 -06001116 goto err_shutdown_phy;
1117 }
1118
1119 ret = eqos_adjust_link(dev);
1120 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001121 pr_err("eqos_adjust_link() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001122 goto err_shutdown_phy;
1123 }
1124
1125 /* Configure MTL */
1126
1127 /* Enable Store and Forward mode for TX */
1128 /* Program Tx operating mode */
1129 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1130 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1131 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1132 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1133
1134 /* Transmit Queue weight */
1135 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1136
1137 /* Enable Store and Forward mode for RX, since no jumbo frame */
1138 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1139 EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
1140
1141 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1142 val = readl(&eqos->mac_regs->hw_feature1);
1143 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1144 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1145 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1146 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1147
1148 /*
1149 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1150 * r/tqs is encoded as (n / 256) - 1.
1151 */
1152 tqs = (128 << tx_fifo_sz) / 256 - 1;
1153 rqs = (128 << rx_fifo_sz) / 256 - 1;
1154
1155 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1156 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1157 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1158 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1159 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1160 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1161 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1162 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1163
1164 /* Flow control used only if each channel gets 4KB or more FIFO */
1165 if (rqs >= ((4096 / 256) - 1)) {
1166 u32 rfd, rfa;
1167
1168 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1169 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1170
1171 /*
1172 * Set Threshold for Activating Flow Contol space for min 2
1173 * frames ie, (1500 * 1) = 1500 bytes.
1174 *
1175 * Set Threshold for Deactivating Flow Contol for space of
1176 * min 1 frame (frame size 1500bytes) in receive fifo
1177 */
1178 if (rqs == ((4096 / 256) - 1)) {
1179 /*
1180 * This violates the above formula because of FIFO size
1181 * limit therefore overflow may occur inspite of this.
1182 */
1183 rfd = 0x3; /* Full-3K */
1184 rfa = 0x1; /* Full-1.5K */
1185 } else if (rqs == ((8192 / 256) - 1)) {
1186 rfd = 0x6; /* Full-4K */
1187 rfa = 0xa; /* Full-6K */
1188 } else if (rqs == ((16384 / 256) - 1)) {
1189 rfd = 0x6; /* Full-4K */
1190 rfa = 0x12; /* Full-10K */
1191 } else {
1192 rfd = 0x6; /* Full-4K */
1193 rfa = 0x1E; /* Full-16K */
1194 }
1195
1196 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1197 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1198 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1199 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1200 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1201 (rfd <<
1202 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1203 (rfa <<
1204 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1205 }
1206
1207 /* Configure MAC */
1208
1209 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1210 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1211 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
Christophe Roullier6beb7802019-05-17 15:08:44 +02001212 eqos->config->config_mac <<
Stephen Warren50709602016-10-21 14:46:47 -06001213 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1214
1215 /* Set TX flow control parameters */
1216 /* Set Pause Time */
1217 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1218 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1219 /* Assign priority for TX flow control */
1220 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1221 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1222 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1223 /* Assign priority for RX flow control */
1224 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1225 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1226 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1227 /* Enable flow control */
1228 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1229 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1230 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1231 EQOS_MAC_RX_FLOW_CTRL_RFE);
1232
1233 clrsetbits_le32(&eqos->mac_regs->configuration,
1234 EQOS_MAC_CONFIGURATION_GPSLCE |
1235 EQOS_MAC_CONFIGURATION_WD |
1236 EQOS_MAC_CONFIGURATION_JD |
1237 EQOS_MAC_CONFIGURATION_JE,
1238 EQOS_MAC_CONFIGURATION_CST |
1239 EQOS_MAC_CONFIGURATION_ACS);
1240
1241 eqos_write_hwaddr(dev);
1242
1243 /* Configure DMA */
1244
1245 /* Enable OSP mode */
1246 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1247 EQOS_DMA_CH0_TX_CONTROL_OSP);
1248
1249 /* RX buffer size. Must be a multiple of bus width */
1250 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1251 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1252 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1253 EQOS_MAX_PACKET_SIZE <<
1254 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1255
1256 setbits_le32(&eqos->dma_regs->ch0_control,
1257 EQOS_DMA_CH0_CONTROL_PBLX8);
1258
1259 /*
1260 * Burst length must be < 1/2 FIFO size.
1261 * FIFO size in tqs is encoded as (n / 256) - 1.
1262 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1263 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1264 */
1265 pbl = tqs + 1;
1266 if (pbl > 32)
1267 pbl = 32;
1268 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1269 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1270 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1271 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1272
1273 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1274 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1275 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1276 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1277
1278 /* DMA performance configuration */
1279 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1280 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1281 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1282 writel(val, &eqos->dma_regs->sysbus_mode);
1283
1284 /* Set up descriptors */
1285
1286 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1287 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1288 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1289 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1290 (i * EQOS_MAX_PACKET_SIZE));
1291 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1292 }
Christophe Roullier6beb7802019-05-17 15:08:44 +02001293 eqos->config->ops->eqos_flush_desc(eqos->descs);
Stephen Warren50709602016-10-21 14:46:47 -06001294
1295 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1296 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1297 writel(EQOS_DESCRIPTORS_TX - 1,
1298 &eqos->dma_regs->ch0_txdesc_ring_length);
1299
1300 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1301 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1302 writel(EQOS_DESCRIPTORS_RX - 1,
1303 &eqos->dma_regs->ch0_rxdesc_ring_length);
1304
1305 /* Enable everything */
1306
1307 setbits_le32(&eqos->mac_regs->configuration,
1308 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1309
1310 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1311 EQOS_DMA_CH0_TX_CONTROL_ST);
1312 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1313 EQOS_DMA_CH0_RX_CONTROL_SR);
1314
1315 /* TX tail pointer not written until we need to TX a packet */
1316 /*
1317 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1318 * first descriptor, implying all descriptors were available. However,
1319 * that's not distinguishable from none of the descriptors being
1320 * available.
1321 */
1322 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1323 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1324
1325 eqos->started = true;
1326
1327 debug("%s: OK\n", __func__);
1328 return 0;
1329
1330err_shutdown_phy:
1331 phy_shutdown(eqos->phy);
Stephen Warren50709602016-10-21 14:46:47 -06001332err_stop_resets:
Christophe Roullier6beb7802019-05-17 15:08:44 +02001333 eqos->config->ops->eqos_stop_resets(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001334err_stop_clks:
Christophe Roullier6beb7802019-05-17 15:08:44 +02001335 eqos->config->ops->eqos_stop_clks(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001336err:
Masahiro Yamada81e10422017-09-16 14:10:41 +09001337 pr_err("FAILED: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001338 return ret;
1339}
1340
Patrick Delaunay6864a5992019-08-01 11:29:02 +02001341static void eqos_stop(struct udevice *dev)
Stephen Warren50709602016-10-21 14:46:47 -06001342{
1343 struct eqos_priv *eqos = dev_get_priv(dev);
1344 int i;
1345
1346 debug("%s(dev=%p):\n", __func__, dev);
1347
1348 if (!eqos->started)
1349 return;
1350 eqos->started = false;
1351 eqos->reg_access_ok = false;
1352
1353 /* Disable TX DMA */
1354 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1355 EQOS_DMA_CH0_TX_CONTROL_ST);
1356
1357 /* Wait for TX all packets to drain out of MTL */
1358 for (i = 0; i < 1000000; i++) {
1359 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1360 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1361 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1362 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1363 if ((trcsts != 1) && (!txqsts))
1364 break;
1365 }
1366
1367 /* Turn off MAC TX and RX */
1368 clrbits_le32(&eqos->mac_regs->configuration,
1369 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1370
1371 /* Wait for all RX packets to drain out of MTL */
1372 for (i = 0; i < 1000000; i++) {
1373 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1374 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1375 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1376 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1377 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1378 if ((!prxq) && (!rxqsts))
1379 break;
1380 }
1381
1382 /* Turn off RX DMA */
1383 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1384 EQOS_DMA_CH0_RX_CONTROL_SR);
1385
1386 if (eqos->phy) {
1387 phy_shutdown(eqos->phy);
Stephen Warren50709602016-10-21 14:46:47 -06001388 }
Christophe Roullier6beb7802019-05-17 15:08:44 +02001389 eqos->config->ops->eqos_stop_resets(dev);
1390 eqos->config->ops->eqos_stop_clks(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001391
1392 debug("%s: OK\n", __func__);
1393}
1394
Patrick Delaunay6864a5992019-08-01 11:29:02 +02001395static int eqos_send(struct udevice *dev, void *packet, int length)
Stephen Warren50709602016-10-21 14:46:47 -06001396{
1397 struct eqos_priv *eqos = dev_get_priv(dev);
1398 struct eqos_desc *tx_desc;
1399 int i;
1400
1401 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1402 length);
1403
1404 memcpy(eqos->tx_dma_buf, packet, length);
Christophe Roullier6beb7802019-05-17 15:08:44 +02001405 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
Stephen Warren50709602016-10-21 14:46:47 -06001406
1407 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1408 eqos->tx_desc_idx++;
1409 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1410
1411 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1412 tx_desc->des1 = 0;
1413 tx_desc->des2 = length;
1414 /*
1415 * Make sure that if HW sees the _OWN write below, it will see all the
1416 * writes to the rest of the descriptor too.
1417 */
1418 mb();
1419 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
Christophe Roullier6beb7802019-05-17 15:08:44 +02001420 eqos->config->ops->eqos_flush_desc(tx_desc);
Stephen Warren50709602016-10-21 14:46:47 -06001421
1422 writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
1423
1424 for (i = 0; i < 1000000; i++) {
Christophe Roullier6beb7802019-05-17 15:08:44 +02001425 eqos->config->ops->eqos_inval_desc(tx_desc);
Stephen Warren50709602016-10-21 14:46:47 -06001426 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1427 return 0;
1428 udelay(1);
1429 }
1430
1431 debug("%s: TX timeout\n", __func__);
1432
1433 return -ETIMEDOUT;
1434}
1435
Patrick Delaunay6864a5992019-08-01 11:29:02 +02001436static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
Stephen Warren50709602016-10-21 14:46:47 -06001437{
1438 struct eqos_priv *eqos = dev_get_priv(dev);
1439 struct eqos_desc *rx_desc;
1440 int length;
1441
1442 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1443
1444 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1445 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1446 debug("%s: RX packet not available\n", __func__);
1447 return -EAGAIN;
1448 }
1449
1450 *packetp = eqos->rx_dma_buf +
1451 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1452 length = rx_desc->des3 & 0x7fff;
1453 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1454
Christophe Roullier6beb7802019-05-17 15:08:44 +02001455 eqos->config->ops->eqos_inval_buffer(*packetp, length);
Stephen Warren50709602016-10-21 14:46:47 -06001456
1457 return length;
1458}
1459
Patrick Delaunay6864a5992019-08-01 11:29:02 +02001460static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
Stephen Warren50709602016-10-21 14:46:47 -06001461{
1462 struct eqos_priv *eqos = dev_get_priv(dev);
1463 uchar *packet_expected;
1464 struct eqos_desc *rx_desc;
1465
1466 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1467
1468 packet_expected = eqos->rx_dma_buf +
1469 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1470 if (packet != packet_expected) {
1471 debug("%s: Unexpected packet (expected %p)\n", __func__,
1472 packet_expected);
1473 return -EINVAL;
1474 }
1475
1476 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1477 rx_desc->des0 = (u32)(ulong)packet;
1478 rx_desc->des1 = 0;
1479 rx_desc->des2 = 0;
1480 /*
1481 * Make sure that if HW sees the _OWN write below, it will see all the
1482 * writes to the rest of the descriptor too.
1483 */
1484 mb();
1485 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
Christophe Roullier6beb7802019-05-17 15:08:44 +02001486 eqos->config->ops->eqos_flush_desc(rx_desc);
Stephen Warren50709602016-10-21 14:46:47 -06001487
1488 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1489
1490 eqos->rx_desc_idx++;
1491 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1492
1493 return 0;
1494}
1495
1496static int eqos_probe_resources_core(struct udevice *dev)
1497{
1498 struct eqos_priv *eqos = dev_get_priv(dev);
1499 int ret;
1500
1501 debug("%s(dev=%p):\n", __func__, dev);
1502
1503 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1504 EQOS_DESCRIPTORS_RX);
1505 if (!eqos->descs) {
1506 debug("%s: eqos_alloc_descs() failed\n", __func__);
1507 ret = -ENOMEM;
1508 goto err;
1509 }
1510 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1511 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1512 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1513 eqos->rx_descs);
1514
1515 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1516 if (!eqos->tx_dma_buf) {
1517 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1518 ret = -ENOMEM;
1519 goto err_free_descs;
1520 }
Christophe Roullier6beb7802019-05-17 15:08:44 +02001521 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
Stephen Warren50709602016-10-21 14:46:47 -06001522
1523 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1524 if (!eqos->rx_dma_buf) {
1525 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1526 ret = -ENOMEM;
1527 goto err_free_tx_dma_buf;
1528 }
Christophe Roullier6beb7802019-05-17 15:08:44 +02001529 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
Stephen Warren50709602016-10-21 14:46:47 -06001530
1531 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1532 if (!eqos->rx_pkt) {
1533 debug("%s: malloc(rx_pkt) failed\n", __func__);
1534 ret = -ENOMEM;
1535 goto err_free_rx_dma_buf;
1536 }
1537 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1538
1539 debug("%s: OK\n", __func__);
1540 return 0;
1541
1542err_free_rx_dma_buf:
1543 free(eqos->rx_dma_buf);
1544err_free_tx_dma_buf:
1545 free(eqos->tx_dma_buf);
1546err_free_descs:
1547 eqos_free_descs(eqos->descs);
1548err:
1549
1550 debug("%s: returns %d\n", __func__, ret);
1551 return ret;
1552}
1553
1554static int eqos_remove_resources_core(struct udevice *dev)
1555{
1556 struct eqos_priv *eqos = dev_get_priv(dev);
1557
1558 debug("%s(dev=%p):\n", __func__, dev);
1559
1560 free(eqos->rx_pkt);
1561 free(eqos->rx_dma_buf);
1562 free(eqos->tx_dma_buf);
1563 eqos_free_descs(eqos->descs);
1564
1565 debug("%s: OK\n", __func__);
1566 return 0;
1567}
1568
1569static int eqos_probe_resources_tegra186(struct udevice *dev)
1570{
1571 struct eqos_priv *eqos = dev_get_priv(dev);
1572 int ret;
1573
1574 debug("%s(dev=%p):\n", __func__, dev);
1575
1576 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1577 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001578 pr_err("reset_get_by_name(rst) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001579 return ret;
1580 }
1581
1582 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1583 &eqos->phy_reset_gpio,
1584 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1585 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001586 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001587 goto err_free_reset_eqos;
1588 }
1589
1590 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1591 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001592 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001593 goto err_free_gpio_phy_reset;
1594 }
1595
1596 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1597 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001598 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001599 goto err_free_clk_slave_bus;
1600 }
1601
1602 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1603 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001604 pr_err("clk_get_by_name(rx) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001605 goto err_free_clk_master_bus;
1606 }
1607
1608 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1609 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001610 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001611 goto err_free_clk_rx;
1612 return ret;
1613 }
1614
1615 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1616 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001617 pr_err("clk_get_by_name(tx) failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001618 goto err_free_clk_ptp_ref;
1619 }
1620
1621 debug("%s: OK\n", __func__);
1622 return 0;
1623
1624err_free_clk_ptp_ref:
1625 clk_free(&eqos->clk_ptp_ref);
1626err_free_clk_rx:
1627 clk_free(&eqos->clk_rx);
1628err_free_clk_master_bus:
1629 clk_free(&eqos->clk_master_bus);
1630err_free_clk_slave_bus:
1631 clk_free(&eqos->clk_slave_bus);
1632err_free_gpio_phy_reset:
1633 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1634err_free_reset_eqos:
1635 reset_free(&eqos->reset_ctl);
1636
1637 debug("%s: returns %d\n", __func__, ret);
1638 return ret;
1639}
1640
Christophe Roullier6beb7802019-05-17 15:08:44 +02001641/* board-specific Ethernet Interface initializations. */
Patrick Delaunaybff66f92019-08-01 11:29:03 +02001642__weak int board_interface_eth_init(struct udevice *dev,
1643 phy_interface_t interface_type)
Christophe Roullier6beb7802019-05-17 15:08:44 +02001644{
1645 return 0;
1646}
1647
1648static int eqos_probe_resources_stm32(struct udevice *dev)
1649{
1650 struct eqos_priv *eqos = dev_get_priv(dev);
1651 int ret;
1652 phy_interface_t interface;
Christophe Roullier104dab52020-03-18 10:50:15 +01001653 struct ofnode_phandle_args phandle_args;
Christophe Roullier6beb7802019-05-17 15:08:44 +02001654
1655 debug("%s(dev=%p):\n", __func__, dev);
1656
1657 interface = eqos->config->interface(dev);
1658
1659 if (interface == PHY_INTERFACE_MODE_NONE) {
1660 pr_err("Invalid PHY interface\n");
1661 return -EINVAL;
1662 }
1663
Patrick Delaunaybff66f92019-08-01 11:29:03 +02001664 ret = board_interface_eth_init(dev, interface);
Christophe Roullier6beb7802019-05-17 15:08:44 +02001665 if (ret)
1666 return -EINVAL;
1667
Patrick Delaunay5c8db372020-03-18 10:50:16 +01001668 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1669
Christophe Roullier6beb7802019-05-17 15:08:44 +02001670 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1671 if (ret) {
1672 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1673 goto err_probe;
1674 }
1675
1676 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1677 if (ret) {
1678 pr_err("clk_get_by_name(rx) failed: %d", ret);
1679 goto err_free_clk_master_bus;
1680 }
1681
1682 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1683 if (ret) {
1684 pr_err("clk_get_by_name(tx) failed: %d", ret);
1685 goto err_free_clk_rx;
1686 }
1687
1688 /* Get ETH_CLK clocks (optional) */
1689 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1690 if (ret)
1691 pr_warn("No phy clock provided %d", ret);
1692
Patrick Delaunay5c8db372020-03-18 10:50:16 +01001693 eqos->phyaddr = -1;
Christophe Roullier104dab52020-03-18 10:50:15 +01001694 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1695 &phandle_args);
1696 if (!ret) {
1697 /* search "reset-gpios" in phy node */
1698 ret = gpio_request_by_name_nodev(phandle_args.node,
1699 "reset-gpios", 0,
1700 &eqos->phy_reset_gpio,
1701 GPIOD_IS_OUT |
1702 GPIOD_IS_OUT_ACTIVE);
1703 if (ret)
1704 pr_warn("gpio_request_by_name(phy reset) not provided %d",
1705 ret);
Patrick Delaunay5c8db372020-03-18 10:50:16 +01001706
1707 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
1708 "reg", -1);
Christophe Roullier104dab52020-03-18 10:50:15 +01001709 }
1710
Christophe Roullier6beb7802019-05-17 15:08:44 +02001711 debug("%s: OK\n", __func__);
1712 return 0;
1713
1714err_free_clk_rx:
1715 clk_free(&eqos->clk_rx);
1716err_free_clk_master_bus:
1717 clk_free(&eqos->clk_master_bus);
1718err_probe:
1719
1720 debug("%s: returns %d\n", __func__, ret);
1721 return ret;
1722}
1723
1724static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1725{
1726 const char *phy_mode;
1727 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1728
1729 debug("%s(dev=%p):\n", __func__, dev);
1730
1731 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1732 NULL);
1733 if (phy_mode)
1734 interface = phy_get_interface_by_name(phy_mode);
1735
1736 return interface;
1737}
1738
1739static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1740{
1741 return PHY_INTERFACE_MODE_MII;
1742}
1743
Stephen Warren50709602016-10-21 14:46:47 -06001744static int eqos_remove_resources_tegra186(struct udevice *dev)
1745{
1746 struct eqos_priv *eqos = dev_get_priv(dev);
1747
1748 debug("%s(dev=%p):\n", __func__, dev);
1749
1750 clk_free(&eqos->clk_tx);
1751 clk_free(&eqos->clk_ptp_ref);
1752 clk_free(&eqos->clk_rx);
1753 clk_free(&eqos->clk_slave_bus);
1754 clk_free(&eqos->clk_master_bus);
1755 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1756 reset_free(&eqos->reset_ctl);
1757
1758 debug("%s: OK\n", __func__);
1759 return 0;
1760}
1761
Christophe Roullier6beb7802019-05-17 15:08:44 +02001762static int eqos_remove_resources_stm32(struct udevice *dev)
1763{
1764 struct eqos_priv *eqos = dev_get_priv(dev);
1765
1766 debug("%s(dev=%p):\n", __func__, dev);
1767
1768 clk_free(&eqos->clk_tx);
1769 clk_free(&eqos->clk_rx);
1770 clk_free(&eqos->clk_master_bus);
1771 if (clk_valid(&eqos->clk_ck))
1772 clk_free(&eqos->clk_ck);
1773
Christophe Roullier104dab52020-03-18 10:50:15 +01001774 if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
1775 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1776
Christophe Roullier6beb7802019-05-17 15:08:44 +02001777 debug("%s: OK\n", __func__);
1778 return 0;
1779}
1780
Stephen Warren50709602016-10-21 14:46:47 -06001781static int eqos_probe(struct udevice *dev)
1782{
1783 struct eqos_priv *eqos = dev_get_priv(dev);
1784 int ret;
1785
1786 debug("%s(dev=%p):\n", __func__, dev);
1787
1788 eqos->dev = dev;
1789 eqos->config = (void *)dev_get_driver_data(dev);
1790
Simon Glassba1dea42017-05-17 17:18:05 -06001791 eqos->regs = devfdt_get_addr(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001792 if (eqos->regs == FDT_ADDR_T_NONE) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001793 pr_err("devfdt_get_addr() failed");
Stephen Warren50709602016-10-21 14:46:47 -06001794 return -ENODEV;
1795 }
1796 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
1797 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
1798 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
1799 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
1800
1801 ret = eqos_probe_resources_core(dev);
1802 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001803 pr_err("eqos_probe_resources_core() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001804 return ret;
1805 }
1806
Christophe Roullier6beb7802019-05-17 15:08:44 +02001807 ret = eqos->config->ops->eqos_probe_resources(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001808 if (ret < 0) {
Christophe Roullier6beb7802019-05-17 15:08:44 +02001809 pr_err("eqos_probe_resources() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001810 goto err_remove_resources_core;
1811 }
1812
1813 eqos->mii = mdio_alloc();
1814 if (!eqos->mii) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001815 pr_err("mdio_alloc() failed");
Christophe Roullier6beb7802019-05-17 15:08:44 +02001816 ret = -ENOMEM;
Stephen Warren50709602016-10-21 14:46:47 -06001817 goto err_remove_resources_tegra;
1818 }
1819 eqos->mii->read = eqos_mdio_read;
1820 eqos->mii->write = eqos_mdio_write;
1821 eqos->mii->priv = eqos;
1822 strcpy(eqos->mii->name, dev->name);
1823
1824 ret = mdio_register(eqos->mii);
1825 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +09001826 pr_err("mdio_register() failed: %d", ret);
Stephen Warren50709602016-10-21 14:46:47 -06001827 goto err_free_mdio;
1828 }
1829
1830 debug("%s: OK\n", __func__);
1831 return 0;
1832
1833err_free_mdio:
1834 mdio_free(eqos->mii);
1835err_remove_resources_tegra:
Christophe Roullier6beb7802019-05-17 15:08:44 +02001836 eqos->config->ops->eqos_remove_resources(dev);
Stephen Warren50709602016-10-21 14:46:47 -06001837err_remove_resources_core:
1838 eqos_remove_resources_core(dev);
1839
1840 debug("%s: returns %d\n", __func__, ret);
1841 return ret;
1842}
1843
1844static int eqos_remove(struct udevice *dev)
1845{
1846 struct eqos_priv *eqos = dev_get_priv(dev);
1847
1848 debug("%s(dev=%p):\n", __func__, dev);
1849
1850 mdio_unregister(eqos->mii);
1851 mdio_free(eqos->mii);
Christophe Roullier6beb7802019-05-17 15:08:44 +02001852 eqos->config->ops->eqos_remove_resources(dev);
1853
Stephen Warren50709602016-10-21 14:46:47 -06001854 eqos_probe_resources_core(dev);
1855
1856 debug("%s: OK\n", __func__);
1857 return 0;
1858}
1859
1860static const struct eth_ops eqos_ops = {
1861 .start = eqos_start,
1862 .stop = eqos_stop,
1863 .send = eqos_send,
1864 .recv = eqos_recv,
1865 .free_pkt = eqos_free_pkt,
1866 .write_hwaddr = eqos_write_hwaddr,
1867};
1868
Christophe Roullier6beb7802019-05-17 15:08:44 +02001869static struct eqos_ops eqos_tegra186_ops = {
1870 .eqos_inval_desc = eqos_inval_desc_tegra186,
1871 .eqos_flush_desc = eqos_flush_desc_tegra186,
1872 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
1873 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
1874 .eqos_probe_resources = eqos_probe_resources_tegra186,
1875 .eqos_remove_resources = eqos_remove_resources_tegra186,
1876 .eqos_stop_resets = eqos_stop_resets_tegra186,
1877 .eqos_start_resets = eqos_start_resets_tegra186,
1878 .eqos_stop_clks = eqos_stop_clks_tegra186,
1879 .eqos_start_clks = eqos_start_clks_tegra186,
1880 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
1881 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
1882 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
1883 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
1884};
1885
Stephen Warren50709602016-10-21 14:46:47 -06001886static const struct eqos_config eqos_tegra186_config = {
1887 .reg_access_always_ok = false,
Christophe Roullier6beb7802019-05-17 15:08:44 +02001888 .mdio_wait = 10,
1889 .swr_wait = 10,
1890 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
1891 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
1892 .interface = eqos_get_interface_tegra186,
1893 .ops = &eqos_tegra186_ops
1894};
1895
1896static struct eqos_ops eqos_stm32_ops = {
1897 .eqos_inval_desc = eqos_inval_desc_stm32,
1898 .eqos_flush_desc = eqos_flush_desc_stm32,
1899 .eqos_inval_buffer = eqos_inval_buffer_stm32,
1900 .eqos_flush_buffer = eqos_flush_buffer_stm32,
1901 .eqos_probe_resources = eqos_probe_resources_stm32,
1902 .eqos_remove_resources = eqos_remove_resources_stm32,
1903 .eqos_stop_resets = eqos_stop_resets_stm32,
1904 .eqos_start_resets = eqos_start_resets_stm32,
1905 .eqos_stop_clks = eqos_stop_clks_stm32,
1906 .eqos_start_clks = eqos_start_clks_stm32,
1907 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
1908 .eqos_disable_calibration = eqos_disable_calibration_stm32,
1909 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
1910 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
1911};
1912
1913static const struct eqos_config eqos_stm32_config = {
1914 .reg_access_always_ok = false,
1915 .mdio_wait = 10000,
1916 .swr_wait = 50,
1917 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
1918 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
1919 .interface = eqos_get_interface_stm32,
1920 .ops = &eqos_stm32_ops
Stephen Warren50709602016-10-21 14:46:47 -06001921};
1922
1923static const struct udevice_id eqos_ids[] = {
1924 {
1925 .compatible = "nvidia,tegra186-eqos",
1926 .data = (ulong)&eqos_tegra186_config
1927 },
Christophe Roullier6beb7802019-05-17 15:08:44 +02001928 {
1929 .compatible = "snps,dwmac-4.20a",
1930 .data = (ulong)&eqos_stm32_config
1931 },
1932
Stephen Warren50709602016-10-21 14:46:47 -06001933 { }
1934};
1935
1936U_BOOT_DRIVER(eth_eqos) = {
1937 .name = "eth_eqos",
1938 .id = UCLASS_ETH,
1939 .of_match = eqos_ids,
1940 .probe = eqos_probe,
1941 .remove = eqos_remove,
1942 .ops = &eqos_ops,
1943 .priv_auto_alloc_size = sizeof(struct eqos_priv),
1944 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1945};