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Thomas Chou7bb1b9b2010-04-20 12:49:52 +08001/*
2 * Altera 10/100/1000 triple speed ethernet mac driver
3 *
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080011#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -070012#include <cpu_func.h>
Thomas Chouec06dd82015-10-22 15:29:11 +080013#include <dm.h>
14#include <errno.h>
15#include <fdt_support.h>
16#include <memalign.h>
17#include <miiphy.h>
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080018#include <net.h>
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080019#include <asm/cache.h>
Masahiro Yamada6373a172020-02-14 16:40:19 +090020#include <linux/dma-mapping.h>
Thomas Chouec06dd82015-10-22 15:29:11 +080021#include <asm/io.h>
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080022#include "altera_tse.h"
23
Thomas Chouec06dd82015-10-22 15:29:11 +080024DECLARE_GLOBAL_DATA_PTR;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080025
Thomas Chouec06dd82015-10-22 15:29:11 +080026static inline void alt_sgdma_construct_descriptor(
27 struct alt_sgdma_descriptor *desc,
28 struct alt_sgdma_descriptor *next,
29 void *read_addr,
30 void *write_addr,
Thomas Chou455e9532015-11-06 09:36:26 +080031 u16 length_or_eop,
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080032 int generate_eop,
33 int read_fixed,
Thomas Chouec06dd82015-10-22 15:29:11 +080034 int write_fixed_or_sop)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080035{
Thomas Chou455e9532015-11-06 09:36:26 +080036 u8 val;
Thomas Chouec06dd82015-10-22 15:29:11 +080037
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080038 /*
39 * Mark the "next" descriptor as "not" owned by hardware. This prevents
Thomas Chouec06dd82015-10-22 15:29:11 +080040 * The SGDMA controller from continuing to process the chain.
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080041 */
Thomas Chouec06dd82015-10-22 15:29:11 +080042 next->descriptor_control = next->descriptor_control &
43 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080044
Thomas Chouec06dd82015-10-22 15:29:11 +080045 memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
46 desc->source = virt_to_phys(read_addr);
47 desc->destination = virt_to_phys(write_addr);
48 desc->next = virt_to_phys(next);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080049 desc->bytes_to_transfer = length_or_eop;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080050
51 /*
52 * Set the descriptor control block as follows:
53 * - Set "owned by hardware" bit
54 * - Optionally set "generate EOP" bit
55 * - Optionally set the "read from fixed address" bit
56 * - Optionally set the "write to fixed address bit (which serves
57 * serves as a "generate SOP" control bit in memory-to-stream mode).
58 * - Set the 4-bit atlantic channel, if specified
59 *
60 * Note this step is performed after all other descriptor information
61 * has been filled out so that, if the controller already happens to be
62 * pointing at this descriptor, it will not run (via the "owned by
63 * hardware" bit) until all other descriptor has been set up.
64 */
Thomas Chouec06dd82015-10-22 15:29:11 +080065 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
66 if (generate_eop)
67 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
68 if (read_fixed)
69 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
70 if (write_fixed_or_sop)
71 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
72 desc->descriptor_control = val;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080073}
74
Thomas Chouec06dd82015-10-22 15:29:11 +080075static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080076{
Thomas Chouec06dd82015-10-22 15:29:11 +080077 int status;
78 ulong ctime;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080079
Thomas Chouec06dd82015-10-22 15:29:11 +080080 /* Wait for the descriptor (chain) to complete */
81 ctime = get_timer(0);
82 while (1) {
83 status = readl(&regs->status);
84 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080085 break;
Thomas Chouec06dd82015-10-22 15:29:11 +080086 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
87 status = -ETIMEDOUT;
88 debug("sgdma timeout\n");
89 break;
90 }
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080091 }
92
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080093 /* Clear Run */
Thomas Chouec06dd82015-10-22 15:29:11 +080094 writel(0, &regs->control);
95 /* Clear status */
96 writel(0xff, &regs->status);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080097
Thomas Chouec06dd82015-10-22 15:29:11 +080098 return status;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +080099}
100
Thomas Chouec06dd82015-10-22 15:29:11 +0800101static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
102 struct alt_sgdma_descriptor *desc)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800103{
Thomas Chou455e9532015-11-06 09:36:26 +0800104 u32 val;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800105
106 /* Point the controller at the descriptor */
Thomas Chouec06dd82015-10-22 15:29:11 +0800107 writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800108
109 /*
110 * Set up SGDMA controller to:
111 * - Disable interrupt generation
112 * - Run once a valid descriptor is written to controller
113 * - Stop on an error with any particular descriptor
114 */
Thomas Chouec06dd82015-10-22 15:29:11 +0800115 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
116 writel(val, &regs->control);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800117
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800118 return 0;
119}
120
Thomas Chouec06dd82015-10-22 15:29:11 +0800121static void tse_adjust_link(struct altera_tse_priv *priv,
122 struct phy_device *phydev)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800123{
Thomas Chouec06dd82015-10-22 15:29:11 +0800124 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chou455e9532015-11-06 09:36:26 +0800125 u32 refvar;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800126
Thomas Chouec06dd82015-10-22 15:29:11 +0800127 if (!phydev->link) {
128 debug("%s: No link.\n", phydev->dev->name);
129 return;
130 }
131
132 refvar = readl(&mac_dev->command_config);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800133
Thomas Chouec06dd82015-10-22 15:29:11 +0800134 if (phydev->duplex)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800135 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
136 else
137 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
138
Thomas Chouec06dd82015-10-22 15:29:11 +0800139 switch (phydev->speed) {
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800140 case 1000:
141 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
142 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
143 break;
144 case 100:
145 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
146 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
147 break;
148 case 10:
149 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
150 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
151 break;
152 }
Thomas Chouec06dd82015-10-22 15:29:11 +0800153 writel(refvar, &mac_dev->command_config);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800154}
155
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800156static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800157{
Thomas Chouec06dd82015-10-22 15:29:11 +0800158 struct altera_tse_priv *priv = dev_get_priv(dev);
159 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800160
Thomas Chouec06dd82015-10-22 15:29:11 +0800161 alt_sgdma_construct_descriptor(
162 tx_desc,
163 tx_desc + 1,
164 packet, /* read addr */
165 NULL, /* write addr */
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800166 length, /* length or EOP ,will change for each tx */
Thomas Chouec06dd82015-10-22 15:29:11 +0800167 1, /* gen eop */
168 0, /* read fixed */
169 1 /* write fixed or sop */
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800170 );
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800171
172 /* send the packet */
Thomas Chouec06dd82015-10-22 15:29:11 +0800173 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
174 alt_sgdma_wait_transfer(priv->sgdma_tx);
175 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
176
177 return tx_desc->actual_bytes_transferred;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800178}
179
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800180static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
181 uchar **packetp)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800182{
Thomas Chouec06dd82015-10-22 15:29:11 +0800183 struct altera_tse_priv *priv = dev_get_priv(dev);
184 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
185 int packet_length;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800186
Thomas Chouec06dd82015-10-22 15:29:11 +0800187 if (rx_desc->descriptor_status &
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800188 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
Thomas Choub917dee2015-11-09 08:00:00 +0800189 alt_sgdma_wait_transfer(priv->sgdma_rx);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800190 packet_length = rx_desc->actual_bytes_transferred;
Thomas Chouec06dd82015-10-22 15:29:11 +0800191 debug("recv %d bytes\n", packet_length);
192 *packetp = priv->rx_buf;
Joachim Foerster384a8192011-10-17 05:24:46 +0000193
194 return packet_length;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800195 }
196
Thomas Chouec06dd82015-10-22 15:29:11 +0800197 return -EAGAIN;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800198}
199
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800200static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
201 int length)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800202{
Thomas Chouec06dd82015-10-22 15:29:11 +0800203 struct altera_tse_priv *priv = dev_get_priv(dev);
204 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
Thomas Chouec06dd82015-10-22 15:29:11 +0800205
Thomas Chouec06dd82015-10-22 15:29:11 +0800206 alt_sgdma_construct_descriptor(
207 rx_desc,
208 rx_desc + 1,
209 NULL, /* read addr */
210 priv->rx_buf, /* write addr */
211 0, /* length or EOP */
212 0, /* gen eop */
213 0, /* read fixed */
214 0 /* write fixed or sop */
215 );
216
217 /* setup the sgdma */
218 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
219 debug("recv setup\n");
220
221 return 0;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800222}
223
Thomas Chou67bd52f2015-11-08 10:57:05 +0800224static void altera_tse_stop_mac(struct altera_tse_priv *priv)
225{
226 struct alt_tse_mac *mac_dev = priv->mac_dev;
227 u32 status;
228 ulong ctime;
229
230 /* reset the mac */
231 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
232 ctime = get_timer(0);
233 while (1) {
234 status = readl(&mac_dev->command_config);
235 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
236 break;
237 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
238 debug("Reset mac timeout\n");
239 break;
240 }
241 }
242}
243
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800244static void altera_tse_stop_sgdma(struct udevice *dev)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800245{
Thomas Chouec06dd82015-10-22 15:29:11 +0800246 struct altera_tse_priv *priv = dev_get_priv(dev);
Thomas Chouec06dd82015-10-22 15:29:11 +0800247 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
248 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
249 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
Thomas Chouec06dd82015-10-22 15:29:11 +0800250 int ret;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800251
252 /* clear rx desc & wait for sgdma to complete */
253 rx_desc->descriptor_control = 0;
Thomas Chouec06dd82015-10-22 15:29:11 +0800254 writel(0, &rx_sgdma->control);
255 ret = alt_sgdma_wait_transfer(rx_sgdma);
256 if (ret == -ETIMEDOUT)
257 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
258 &rx_sgdma->control);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800259
Thomas Chouec06dd82015-10-22 15:29:11 +0800260 writel(0, &tx_sgdma->control);
261 ret = alt_sgdma_wait_transfer(tx_sgdma);
262 if (ret == -ETIMEDOUT)
263 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
264 &tx_sgdma->control);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800265}
266
Thomas Chou9c0a2012015-11-09 14:36:29 +0800267static void msgdma_reset(struct msgdma_csr *csr)
268{
269 u32 status;
270 ulong ctime;
271
272 /* Reset mSGDMA */
273 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
274 writel(MSGDMA_CSR_CTL_RESET, &csr->control);
275 ctime = get_timer(0);
276 while (1) {
277 status = readl(&csr->status);
278 if (!(status & MSGDMA_CSR_STAT_RESETTING))
279 break;
280 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
281 debug("Reset msgdma timeout\n");
282 break;
283 }
284 }
285 /* Clear status */
286 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
287}
288
289static u32 msgdma_wait(struct msgdma_csr *csr)
290{
291 u32 status;
292 ulong ctime;
293
294 /* Wait for the descriptor to complete */
295 ctime = get_timer(0);
296 while (1) {
297 status = readl(&csr->status);
298 if (!(status & MSGDMA_CSR_STAT_BUSY))
299 break;
300 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
301 debug("sgdma timeout\n");
302 break;
303 }
304 }
305 /* Clear status */
306 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
307
308 return status;
309}
310
311static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
312 int length)
313{
314 struct altera_tse_priv *priv = dev_get_priv(dev);
315 struct msgdma_extended_desc *desc = priv->tx_desc;
316 u32 tx_buf = virt_to_phys(packet);
317 u32 status;
318
319 writel(tx_buf, &desc->read_addr_lo);
320 writel(0, &desc->read_addr_hi);
321 writel(0, &desc->write_addr_lo);
322 writel(0, &desc->write_addr_hi);
323 writel(length, &desc->len);
324 writel(0, &desc->burst_seq_num);
325 writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
326 writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
327 status = msgdma_wait(priv->sgdma_tx);
328 debug("sent %d bytes, status %08x\n", length, status);
329
330 return 0;
331}
332
333static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
334 uchar **packetp)
335{
336 struct altera_tse_priv *priv = dev_get_priv(dev);
337 struct msgdma_csr *csr = priv->sgdma_rx;
338 struct msgdma_response *resp = priv->rx_resp;
339 u32 level, length, status;
340
341 level = readl(&csr->resp_fill_level);
342 if (level & 0xffff) {
343 length = readl(&resp->bytes_transferred);
344 status = readl(&resp->status);
345 debug("recv %d bytes, status %08x\n", length, status);
346 *packetp = priv->rx_buf;
347
348 return length;
349 }
350
351 return -EAGAIN;
352}
353
354static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
355 int length)
356{
357 struct altera_tse_priv *priv = dev_get_priv(dev);
358 struct msgdma_extended_desc *desc = priv->rx_desc;
359 u32 rx_buf = virt_to_phys(priv->rx_buf);
360
361 writel(0, &desc->read_addr_lo);
362 writel(0, &desc->read_addr_hi);
363 writel(rx_buf, &desc->write_addr_lo);
364 writel(0, &desc->write_addr_hi);
365 writel(PKTSIZE_ALIGN, &desc->len);
366 writel(0, &desc->burst_seq_num);
367 writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
368 writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
369 debug("recv setup\n");
370
371 return 0;
372}
373
374static void altera_tse_stop_msgdma(struct udevice *dev)
375{
376 struct altera_tse_priv *priv = dev_get_priv(dev);
377
378 msgdma_reset(priv->sgdma_rx);
379 msgdma_reset(priv->sgdma_tx);
380}
381
Thomas Chouec06dd82015-10-22 15:29:11 +0800382static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800383{
Thomas Chouec06dd82015-10-22 15:29:11 +0800384 struct altera_tse_priv *priv = bus->priv;
385 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chou455e9532015-11-06 09:36:26 +0800386 u32 value;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800387
388 /* set mdio address */
Thomas Chouec06dd82015-10-22 15:29:11 +0800389 writel(addr, &mac_dev->mdio_phy1_addr);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800390 /* get the data */
Thomas Chouec06dd82015-10-22 15:29:11 +0800391 value = readl(&mac_dev->mdio_phy1[reg]);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800392
Thomas Chouec06dd82015-10-22 15:29:11 +0800393 return value & 0xffff;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800394}
395
Thomas Chouec06dd82015-10-22 15:29:11 +0800396static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
397 u16 val)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800398{
Thomas Chouec06dd82015-10-22 15:29:11 +0800399 struct altera_tse_priv *priv = bus->priv;
400 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800401
402 /* set mdio address */
Thomas Chouec06dd82015-10-22 15:29:11 +0800403 writel(addr, &mac_dev->mdio_phy1_addr);
404 /* set the data */
405 writel(val, &mac_dev->mdio_phy1[reg]);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800406
407 return 0;
408}
409
Thomas Chouec06dd82015-10-22 15:29:11 +0800410static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800411{
Thomas Chouec06dd82015-10-22 15:29:11 +0800412 struct mii_dev *bus = mdio_alloc();
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800413
Thomas Chouec06dd82015-10-22 15:29:11 +0800414 if (!bus) {
415 printf("Failed to allocate MDIO bus\n");
416 return -ENOMEM;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800417 }
418
Thomas Chouec06dd82015-10-22 15:29:11 +0800419 bus->read = tse_mdio_read;
420 bus->write = tse_mdio_write;
Ben Whitten34fd6c92015-12-30 13:05:58 +0000421 snprintf(bus->name, sizeof(bus->name), "%s", name);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800422
Thomas Chouec06dd82015-10-22 15:29:11 +0800423 bus->priv = (void *)priv;
Joachim Foerster7ce99292011-10-25 22:39:57 +0000424
Thomas Chouec06dd82015-10-22 15:29:11 +0800425 return mdio_register(bus);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800426}
427
Thomas Chouec06dd82015-10-22 15:29:11 +0800428static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800429{
Thomas Chouec06dd82015-10-22 15:29:11 +0800430 struct phy_device *phydev;
431 unsigned int mask = 0xffffffff;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800432
Thomas Chouec06dd82015-10-22 15:29:11 +0800433 if (priv->phyaddr)
434 mask = 1 << priv->phyaddr;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800435
Thomas Chouec06dd82015-10-22 15:29:11 +0800436 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
437 if (!phydev)
438 return -ENODEV;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800439
Thomas Chouec06dd82015-10-22 15:29:11 +0800440 phy_connect_dev(phydev, dev);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800441
Thomas Chouec06dd82015-10-22 15:29:11 +0800442 phydev->supported &= PHY_GBIT_FEATURES;
443 phydev->advertising = phydev->supported;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800444
Thomas Chouec06dd82015-10-22 15:29:11 +0800445 priv->phydev = phydev;
446 phy_config(phydev);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800447
Thomas Chouec06dd82015-10-22 15:29:11 +0800448 return 0;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800449}
450
Thomas Chouec06dd82015-10-22 15:29:11 +0800451static int altera_tse_write_hwaddr(struct udevice *dev)
Thomas Chou53d01502010-04-27 20:15:10 +0800452{
Thomas Chouec06dd82015-10-22 15:29:11 +0800453 struct altera_tse_priv *priv = dev_get_priv(dev);
454 struct alt_tse_mac *mac_dev = priv->mac_dev;
455 struct eth_pdata *pdata = dev_get_platdata(dev);
456 u8 *hwaddr = pdata->enetaddr;
Thomas Chou455e9532015-11-06 09:36:26 +0800457 u32 mac_lo, mac_hi;
Thomas Chou53d01502010-04-27 20:15:10 +0800458
Thomas Chouec06dd82015-10-22 15:29:11 +0800459 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
460 (hwaddr[1] << 8) | hwaddr[0];
461 mac_hi = (hwaddr[5] << 8) | hwaddr[4];
462 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
Thomas Chou53d01502010-04-27 20:15:10 +0800463
Thomas Chouec06dd82015-10-22 15:29:11 +0800464 writel(mac_lo, &mac_dev->mac_addr_0);
465 writel(mac_hi, &mac_dev->mac_addr_1);
466 writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
467 writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
468 writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
469 writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
470 writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
471 writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
472 writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
473 writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
Thomas Chou53d01502010-04-27 20:15:10 +0800474
Thomas Chou53d01502010-04-27 20:15:10 +0800475 return 0;
476}
477
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800478static int altera_tse_send(struct udevice *dev, void *packet, int length)
479{
480 struct altera_tse_priv *priv = dev_get_priv(dev);
481 unsigned long tx_buf = (unsigned long)packet;
482
483 flush_dcache_range(tx_buf, tx_buf + length);
484
485 return priv->ops->send(dev, packet, length);
486}
487
488static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
489{
490 struct altera_tse_priv *priv = dev_get_priv(dev);
491
492 return priv->ops->recv(dev, flags, packetp);
493}
494
495static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
496 int length)
497{
498 struct altera_tse_priv *priv = dev_get_priv(dev);
499 unsigned long rx_buf = (unsigned long)priv->rx_buf;
500
501 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
502
503 return priv->ops->free_pkt(dev, packet, length);
504}
505
506static void altera_tse_stop(struct udevice *dev)
507{
508 struct altera_tse_priv *priv = dev_get_priv(dev);
509
510 priv->ops->stop(dev);
511 altera_tse_stop_mac(priv);
512}
513
Thomas Chouec06dd82015-10-22 15:29:11 +0800514static int altera_tse_start(struct udevice *dev)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800515{
Thomas Chouec06dd82015-10-22 15:29:11 +0800516 struct altera_tse_priv *priv = dev_get_priv(dev);
517 struct alt_tse_mac *mac_dev = priv->mac_dev;
Thomas Chou455e9532015-11-06 09:36:26 +0800518 u32 val;
Thomas Chouec06dd82015-10-22 15:29:11 +0800519 int ret;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800520
521 /* need to create sgdma */
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800522 debug("Configuring rx desc\n");
Thomas Chouec06dd82015-10-22 15:29:11 +0800523 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800524 /* start TSE */
525 debug("Configuring TSE Mac\n");
526 /* Initialize MAC registers */
Thomas Chouec06dd82015-10-22 15:29:11 +0800527 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
528 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
529 writel(0, &mac_dev->rx_sel_full_threshold);
530 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
531 writel(0, &mac_dev->tx_sel_full_threshold);
532 writel(8, &mac_dev->rx_almost_empty_threshold);
533 writel(8, &mac_dev->rx_almost_full_threshold);
534 writel(8, &mac_dev->tx_almost_empty_threshold);
535 writel(3, &mac_dev->tx_almost_full_threshold);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800536
537 /* NO Shift */
Thomas Chouec06dd82015-10-22 15:29:11 +0800538 writel(0, &mac_dev->rx_cmd_stat);
539 writel(0, &mac_dev->tx_cmd_stat);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800540
541 /* enable MAC */
Thomas Chouec06dd82015-10-22 15:29:11 +0800542 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
543 writel(val, &mac_dev->command_config);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800544
Thomas Chouec06dd82015-10-22 15:29:11 +0800545 /* Start up the PHY */
546 ret = phy_startup(priv->phydev);
547 if (ret) {
548 debug("Could not initialize PHY %s\n",
549 priv->phydev->dev->name);
550 return ret;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800551 }
552
Thomas Chouec06dd82015-10-22 15:29:11 +0800553 tse_adjust_link(priv, priv->phydev);
554
555 if (!priv->phydev->link)
556 return -EIO;
557
558 return 0;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800559}
560
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800561static const struct tse_ops tse_sgdma_ops = {
562 .send = altera_tse_send_sgdma,
563 .recv = altera_tse_recv_sgdma,
564 .free_pkt = altera_tse_free_pkt_sgdma,
565 .stop = altera_tse_stop_sgdma,
566};
567
Thomas Chou9c0a2012015-11-09 14:36:29 +0800568static const struct tse_ops tse_msgdma_ops = {
569 .send = altera_tse_send_msgdma,
570 .recv = altera_tse_recv_msgdma,
571 .free_pkt = altera_tse_free_pkt_msgdma,
572 .stop = altera_tse_stop_msgdma,
573};
574
Thomas Chouec06dd82015-10-22 15:29:11 +0800575static int altera_tse_probe(struct udevice *dev)
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800576{
Thomas Chouec06dd82015-10-22 15:29:11 +0800577 struct eth_pdata *pdata = dev_get_platdata(dev);
578 struct altera_tse_priv *priv = dev_get_priv(dev);
Thomas Choudde1ffb2015-11-06 09:37:17 +0800579 void *blob = (void *)gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700580 int node = dev_of_offset(dev);
Thomas Chouec06dd82015-10-22 15:29:11 +0800581 const char *list, *end;
582 const fdt32_t *cell;
583 void *base, *desc_mem = NULL;
584 unsigned long addr, size;
Thomas Choudde1ffb2015-11-06 09:37:17 +0800585 int parent, addrc, sizec;
Thomas Chouec06dd82015-10-22 15:29:11 +0800586 int len, idx;
587 int ret;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800588
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800589 priv->dma_type = dev_get_driver_data(dev);
590 if (priv->dma_type == ALT_SGDMA)
591 priv->ops = &tse_sgdma_ops;
Thomas Chou9c0a2012015-11-09 14:36:29 +0800592 else
593 priv->ops = &tse_msgdma_ops;
Thomas Chouec06dd82015-10-22 15:29:11 +0800594 /*
Thomas Choudde1ffb2015-11-06 09:37:17 +0800595 * decode regs. there are multiple reg tuples, and they need to
596 * match with reg-names.
Thomas Chouec06dd82015-10-22 15:29:11 +0800597 */
Thomas Choudde1ffb2015-11-06 09:37:17 +0800598 parent = fdt_parent_offset(blob, node);
Simon Glassbb7c01e2017-05-18 20:09:26 -0600599 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
Thomas Chouec06dd82015-10-22 15:29:11 +0800600 list = fdt_getprop(blob, node, "reg-names", &len);
601 if (!list)
602 return -ENOENT;
603 end = list + len;
604 cell = fdt_getprop(blob, node, "reg", &len);
605 if (!cell)
606 return -ENOENT;
607 idx = 0;
608 while (list < end) {
609 addr = fdt_translate_address((void *)blob,
610 node, cell + idx);
Thomas Choudde1ffb2015-11-06 09:37:17 +0800611 size = fdt_addr_to_cpu(cell[idx + addrc]);
Thomas Choufb468332015-11-14 11:21:16 +0800612 base = map_physmem(addr, size, MAP_NOCACHE);
Thomas Chouec06dd82015-10-22 15:29:11 +0800613 len = strlen(list);
614 if (strcmp(list, "control_port") == 0)
615 priv->mac_dev = base;
616 else if (strcmp(list, "rx_csr") == 0)
617 priv->sgdma_rx = base;
Thomas Chou9c0a2012015-11-09 14:36:29 +0800618 else if (strcmp(list, "rx_desc") == 0)
619 priv->rx_desc = base;
620 else if (strcmp(list, "rx_resp") == 0)
621 priv->rx_resp = base;
Thomas Chouec06dd82015-10-22 15:29:11 +0800622 else if (strcmp(list, "tx_csr") == 0)
623 priv->sgdma_tx = base;
Thomas Chou9c0a2012015-11-09 14:36:29 +0800624 else if (strcmp(list, "tx_desc") == 0)
625 priv->tx_desc = base;
Thomas Chouec06dd82015-10-22 15:29:11 +0800626 else if (strcmp(list, "s1") == 0)
627 desc_mem = base;
Thomas Choudde1ffb2015-11-06 09:37:17 +0800628 idx += addrc + sizec;
Thomas Chouec06dd82015-10-22 15:29:11 +0800629 list += (len + 1);
630 }
631 /* decode fifo depth */
632 priv->rx_fifo_depth = fdtdec_get_int(blob, node,
633 "rx-fifo-depth", 0);
634 priv->tx_fifo_depth = fdtdec_get_int(blob, node,
635 "tx-fifo-depth", 0);
636 /* decode phy */
637 addr = fdtdec_get_int(blob, node,
638 "phy-handle", 0);
639 addr = fdt_node_offset_by_phandle(blob, addr);
640 priv->phyaddr = fdtdec_get_int(blob, addr,
641 "reg", 0);
642 /* init desc */
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800643 if (priv->dma_type == ALT_SGDMA) {
644 len = sizeof(struct alt_sgdma_descriptor) * 4;
645 if (!desc_mem) {
646 desc_mem = dma_alloc_coherent(len, &addr);
647 if (!desc_mem)
648 return -ENOMEM;
649 }
650 memset(desc_mem, 0, len);
651 priv->tx_desc = desc_mem;
652 priv->rx_desc = priv->tx_desc +
653 2 * sizeof(struct alt_sgdma_descriptor);
Thomas Chouec06dd82015-10-22 15:29:11 +0800654 }
Thomas Chouec06dd82015-10-22 15:29:11 +0800655 /* allocate recv packet buffer */
656 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
657 if (!priv->rx_buf)
658 return -ENOMEM;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800659
Thomas Chouec06dd82015-10-22 15:29:11 +0800660 /* stop controller */
661 debug("Reset TSE & SGDMAs\n");
662 altera_tse_stop(dev);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800663
Thomas Chouec06dd82015-10-22 15:29:11 +0800664 /* start the phy */
665 priv->interface = pdata->phy_interface;
666 tse_mdio_init(dev->name, priv);
667 priv->bus = miiphy_get_dev_by_name(dev->name);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800668
Thomas Chouec06dd82015-10-22 15:29:11 +0800669 ret = tse_phy_init(priv, dev);
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800670
Thomas Chouec06dd82015-10-22 15:29:11 +0800671 return ret;
672}
Joachim Foerstercb0ddaf2011-10-17 05:24:44 +0000673
Thomas Chouec06dd82015-10-22 15:29:11 +0800674static int altera_tse_ofdata_to_platdata(struct udevice *dev)
675{
676 struct eth_pdata *pdata = dev_get_platdata(dev);
677 const char *phy_mode;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800678
Thomas Chouec06dd82015-10-22 15:29:11 +0800679 pdata->phy_interface = -1;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700680 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
681 NULL);
Thomas Chouec06dd82015-10-22 15:29:11 +0800682 if (phy_mode)
683 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
684 if (pdata->phy_interface == -1) {
685 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
686 return -EINVAL;
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800687 }
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800688
Thomas Chouec06dd82015-10-22 15:29:11 +0800689 return 0;
690}
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800691
Thomas Chouec06dd82015-10-22 15:29:11 +0800692static const struct eth_ops altera_tse_ops = {
693 .start = altera_tse_start,
694 .send = altera_tse_send,
695 .recv = altera_tse_recv,
696 .free_pkt = altera_tse_free_pkt,
697 .stop = altera_tse_stop,
698 .write_hwaddr = altera_tse_write_hwaddr,
699};
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800700
Thomas Chouec06dd82015-10-22 15:29:11 +0800701static const struct udevice_id altera_tse_ids[] = {
Thomas Chou9c0a2012015-11-09 14:36:29 +0800702 { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
Thomas Chou9f9d66a2015-11-09 11:02:15 +0800703 { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
704 {}
Thomas Chouec06dd82015-10-22 15:29:11 +0800705};
Thomas Chou7bb1b9b2010-04-20 12:49:52 +0800706
Thomas Chouec06dd82015-10-22 15:29:11 +0800707U_BOOT_DRIVER(altera_tse) = {
708 .name = "altera_tse",
709 .id = UCLASS_ETH,
710 .of_match = altera_tse_ids,
711 .ops = &altera_tse_ops,
712 .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
713 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
714 .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
715 .probe = altera_tse_probe,
716};