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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andreas Färber9e3ad682017-05-15 17:51:18 +08002/*
3 * Copyright (c) 2016 Andreas Färber
Andreas Färber9e3ad682017-05-15 17:51:18 +08004 */
5
6#ifndef __CONFIG_RK3368_COMMON_H
7#define __CONFIG_RK3368_COMMON_H
8
Klaus Gogera850b2b2017-10-06 19:24:09 +02009#include "rockchip-common.h"
10
Andreas Färber9e3ad682017-05-15 17:51:18 +080011#define CONFIG_SYS_CACHELINE_SIZE 64
12
13#include <asm/arch/hardware.h>
14#include <linux/sizes.h>
15
Kever Yang5db9e672017-06-23 16:11:05 +080016#define CONFIG_SYS_SDRAM_BASE 0
17#define SDRAM_MAX_SIZE 0xff000000
Andreas Färber9e3ad682017-05-15 17:51:18 +080018#define CONFIG_BAUDRATE 115200
19#define CONFIG_SYS_MALLOC_LEN (32 << 20)
20#define CONFIG_SYS_CBSIZE 1024
21#define CONFIG_SKIP_LOWLEVEL_INIT
22
Philipp Tomsich9b687c72017-06-22 23:31:55 +020023#define COUNTER_FREQUENCY 24000000
24
Andreas Färber9e3ad682017-05-15 17:51:18 +080025#define CONFIG_SYS_NS16550_MEM32
26
Andreas Färber9e3ad682017-05-15 17:51:18 +080027#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
28#define CONFIG_SYS_LOAD_ADDR 0x00280000
29
Philipp Tomsich0c1c09f2017-07-14 17:52:09 +020030#define CONFIG_SPL_TEXT_BASE 0x00000000
31#define CONFIG_SPL_MAX_SIZE 0x40000
32#define CONFIG_SPL_BSS_START_ADDR 0x400000
33#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
34
Andreas Färber9e3ad682017-05-15 17:51:18 +080035#define CONFIG_BOUNCE_BUFFER
36
37#ifndef CONFIG_SPL_BUILD
38#define ENV_MEM_LAYOUT_SETTINGS \
39 "scriptaddr=0x00500000\0" \
40 "pxefile_addr_r=0x00600000\0" \
41 "fdt_addr_r=0x5600000\0" \
42 "kernel_addr_r=0x280000\0" \
43 "ramdisk_addr_r=0x5bf0000\0"
44
Andreas Färber9e3ad682017-05-15 17:51:18 +080045#include <config_distro_bootcmd.h>
46
47#define CONFIG_EXTRA_ENV_SETTINGS \
Klaus Goger2b6b4f22018-05-25 23:45:05 +020048 "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
Andy Yanc35846d2017-09-04 20:32:23 +080049 ENV_MEM_LAYOUT_SETTINGS \
Andreas Färber9e3ad682017-05-15 17:51:18 +080050 BOOTENV
51
52#endif
53
54#endif