blob: af7a3ce9c1a61c89f7c9eff3b1a1ed4530e53bbe [file] [log] [blame]
Michal Simek0793f382023-09-27 11:53:30 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)
4 *
5 * (C) Copyright 2019 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12/plugin/;
13
14/{
15 compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03";
16
17 fragment@0 {
18 target = <&dc_i2c>;
19
20 __overlay__ {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 x_prc_eeprom: eeprom@52 { /* u1 */
25 compatible = "atmel,24c02";
26 reg = <0x52>;
27 };
28
29 x_prc_tca9534: gpio@22 { /* u3 tca9534 */
30 compatible = "nxp,pca9534";
31 reg = <0x22>;
32 gpio-controller; /* IRQ not connected */
33 #gpio-cells = <2>;
34 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
35 "", "", "", "";
36 gtr-sel0 {
37 gpio-hog;
38 gpios = <0 0>;
39 input; /* FIXME add meaning */
40 line-name = "sw4_1";
41 };
42 gtr-sel1 {
43 gpio-hog;
44 gpios = <1 0>;
45 input; /* FIXME add meaning */
46 line-name = "sw4_2";
47 };
48 gtr-sel2 {
49 gpio-hog;
50 gpios = <2 0>;
51 input; /* FIXME add meaning */
52 line-name = "sw4_3";
53 };
54 gtr-sel3 {
55 gpio-hog;
56 gpios = <3 0>;
57 input; /* FIXME add meaning */
58 line-name = "sw4_4";
59 };
60 };
61 x_prc_si5338: clock-generator@70 { /* U9 */
62 compatible = "silabs,si5338";
63 reg = <0x70>; /* FIXME */
64 };
65 };
66 };
67
68 fragment@1 {
69 target = <&i2c1>; /* Must be enabled via J90/J91 */
70 __overlay__ {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 eeprom_versal: eeprom@51 { /* u2 */
75 compatible = "atmel,24c02";
76 reg = <0x51>;
77 };
78 };
79 };
80};