blob: 0ae9f91fbe8a38bc7c9aebf19bb3bfc949192f9e [file] [log] [blame]
Chris Brandt1f3b6672017-08-23 14:53:59 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source extras for U-Boot for the GR Peach board
4 *
5 * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8#include "r7s72100-gr-peach.dts"
9
10/ {
11 aliases {
12 spi0 = &rpc;
13 };
14
15 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -070016 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050017 };
18
19 leds {
20 led1 {
21 label = "peach:bottom:red";
22 };
23
24 led-red {
25 label = "peach:tri:red";
26 gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
27 };
28
29 led-green {
30 label = "peach:tri:green";
31 gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
32 };
33
34 led-blue {
35 label = "peach:tri:blue";
36 gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
37 };
38 };
39
Marek Vasut4c5fee02019-08-11 13:22:32 +020040 reg_usbhs0_vbus: regulator-usbhs0-vbus {
41 compatible = "regulator-fixed";
42 regulator-name = "usbhs0_vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 gpio = <&port4 1 GPIO_ACTIVE_LOW>;
46 };
47
48
Geert Uytterhoeven6bf83652022-03-29 14:19:07 +020049 rpc: spi@ee200000 {
Geert Uytterhoeven431ded62022-03-29 14:19:09 +020050 compatible = "renesas,r7s72100-rpc-if";
Chris Brandt1f3b6672017-08-23 14:53:59 -050051 reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
52 bank-width = <2>;
53 num-cs = <1>;
54 status = "okay";
55 spi-max-frequency = <50000000>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 flash0: spi-flash@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "jedec,spi-nor";
63 spi-max-frequency = <50000000>;
64 spi-tx-bus-width = <1>;
65 spi-rx-bus-width = <1>;
66 reg = <0>;
67 status = "okay";
68 };
69 };
70};
71
72&ostm0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070073 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050074};
75
76&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -070077 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050078};
79
80&scif2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070081 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050082 clock = <66666666>; /* ToDo: Replace by DM clock driver */
83};
84
85&scif2_pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -070086 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050087};
Marek Vasut4c5fee02019-08-11 13:22:32 +020088
89&usbhs0 {
90 vbus-supply = <&reg_usbhs0_vbus>;
91 status = "okay";
92};