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git01.mediatek.com / filogic / uboot / 86ddc967b259a5b73865663a741639fa7c3e032c / . / arch / arm / dts / imx8qm-dmsse20-a1.dts
blob: cff150de07c043c25a8e1fac2c5e971c34c40cec [file] [log] [blame]
Oliver Grauteabf0e7b2023-04-21 12:11:50 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2017-2018 NXP
4 * Copyright 2019-2023 Kococonnector GmbH
5 */
6
7/dts-v1/;
8
9/* First 128KB is for PSCI ATF. */
10/memreserve/ 0x80000000 0x00020000;
11
12#include "fsl-imx8qm.dtsi"
13#include "imx8qm-u-boot.dtsi"
14
15/ {
16 model = "Advantech iMX8QM DMSSE20";
17 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
18
19 aliases {
20 mmc0 = &usdhc1;
21 mmc2 = &usdhc3;
22 };
23
24 chosen {
25 bootargs = "console=ttyLP0,115200 earlycon";
26 stdout-path = &lpuart0;
27 };
28
29 reg_usb_otg1_vbus: usb_otg1_vbus {
30 compatible = "regulator-fixed";
31 regulator-name = "usb_otg1_vbus";
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
34 gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
35 enable-active-high;
36 };
37
38 reg_usdhc2_vmmc: usdhc2_vmmc {
39 compatible = "regulator-fixed";
40 regulator-name = "sw-3p3-sd1";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
44 enable-active-high;
45 };
46};
47
48&iomuxc {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_hog>;
51
52 imx8qm-mek {
53 pinctrl_hog: hoggrp {
54 fsl,pins = <
55 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
56 >;
57 };
58
59 pinctrl_fec1: fec1grp {
60 fsl,pins = <
61 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
62 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
63 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
64 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
65 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
66 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
67 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
68 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
69 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
70 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
71 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
72 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
73 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
74 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
75 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
76 >;
77 };
78
79 pinctrl_fec2: fec2grp {
80 fsl,pins = <
81 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
82 SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020
83 SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020
84 SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
85 SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
86 SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
87 SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
88 SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
89 SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
90 SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
91 SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
92 SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
93 SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
94 SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
95 SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
96 >;
97 };
98
99 pinctrl_lpi2c1: lpi2c1grp {
100 fsl,pins = <
101 SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
102 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
103 >;
104 };
105
106 pinctrl_lpi2c2: lpi2c2grp {
107 fsl,pins = <
108 SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c
109 SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c
110 >;
111 };
112
113 pinctrl_lpuart0: lpuart0grp {
114 fsl,pins = <
115 SC_P_UART0_RX_DMA_UART0_RX 0x06000020
116 SC_P_UART0_TX_DMA_UART0_TX 0x06000020
117 >;
118 };
119
120 pinctrl_rtc_mc_8803: rtc-mc-8803-grp{
121 fsl,pins = <
122 SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c
123 SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c
124 >;
125 };
126
127 pinctrl_usdhc1: usdhc1grp {
128 fsl,pins = <
129 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
130 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
131 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
132 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
133 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
134 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
135 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
136 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
137 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
138 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
139 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
140 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
141 >;
142 };
143
144 pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
145 fsl,pins = <
146 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
147 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
148 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
149 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
150 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
151 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
152 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
153 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
154 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
155 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
156 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
157 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
158 >;
159 };
160
161 pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
162 fsl,pins = <
163 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
164 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
165 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
166 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
167 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
168 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
169 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
170 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
171 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
172 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
173 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
174 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
175 >;
176 };
177
178 pinctrl_usdhc2_gpio: usdhc2grpgpio {
179 fsl,pins = <
180 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020
181 SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020
182 >;
183 };
184
185 pinctrl_usdhc3_gpio: usdhc3grpgpio {
186 fsl,pins = <
187 SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
188 SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
189 >;
190 };
191
192 pinctrl_usdhc2: usdhc2grp {
193 fsl,pins = <
194 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
195 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
196 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
197 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
198 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
199 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
200 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
201 >;
202 };
203
204 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
205 fsl,pins = <
206 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
207 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
208 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
209 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
210 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
211 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
212 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
213 >;
214 };
215
216 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
217 fsl,pins = <
218 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
219 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
220 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
221 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
222 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
223 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
224 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
225 >;
226 };
227
228 pinctrl_usdhc3: usdhc3grp {
229 fsl,pins = <
230 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
231 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
232 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
233 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
234 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
235 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
236 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
237 >;
238 };
239
240 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
241 fsl,pins = <
242 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
243 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
244 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
245 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
246 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
247 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
248 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
249 >;
250 };
251
252 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
253 fsl,pins = <
254 SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
255 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
256 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
257 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
258 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
259 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
260 SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
261 >;
262 };
263 };
264};
265
266&gpio2 {
267 status = "okay";
268};
269
270&gpio4 {
271 status = "okay";
272};
273
274&gpio5 {
275 status = "okay";
276};
277
278&usdhc1 {
279 bus-width = <8>;
280 non-removable;
281 pinctrl-names = "default", "state_100mhz", "state_200mhz";
282 pinctrl-0 = <&pinctrl_usdhc1>;
283 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
284 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
285 status = "okay";
286};
287
288&usdhc2 {
289 bus-width = <4>;
290 cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
291 pinctrl-names = "default", "state_100mhz", "state_200mhz";
292 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
293 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
294 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
295 wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
296 vmmc-supply = <&reg_usdhc2_vmmc>;
297 status = "okay";
298};
299
300&usdhc3 {
301 bus-width = <4>;
302 cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
303 no-1-8-v;
304 pinctrl-names = "default","state_100mhz", "state_200mhz";
305 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
306 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
307 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
308 wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
309 status = "okay";
310};
311
312&fec1 {
313 fsl,ar8031-phy-fixup;
314 fsl,magic-packet;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_fec1>;
317 phy-mode = "rgmii-id";
318 phy-handle = <&ethphy0>;
319 status = "okay";
320
321 mdio {
322 #address-cells = <1>;
323 #size-cells = <0>;
324
325 ethphy0: ethernet-phy@4 {
326 compatible = "ethernet-phy-ieee802.3-c22";
327 reg = <4>;
328 };
329 };
330};
331
332&fec2 {
333 fsl,ar8031-phy-fixup;
334 fsl,magic-packet;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_fec2>;
337 phy-mode = "rgmii-id";
338 phy-handle = <&ethphy1>;
339 status = "okay";
340
341 mdio {
342 #address-cells = <1>;
343 #size-cells = <0>;
344
345 ethphy1: ethernet-phy@4 {
346 compatible = "ethernet-phy-ieee802.3-c22";
347 reg = <4>;
348 };
349 };
350};
351
352&i2c1 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 clock-frequency = <100000>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_lpi2c1>;
358 status = "okay";
359};
360
361&i2c2 {
362 #address-cells = <1>;
363 #size-cells = <0>;
364 clock-frequency = <100000>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_lpi2c2>;
367 status = "okay";
368};
369
370&i2c3 {
371 #address-cells = <1>;
372 #size-cells = <0>;
373 clock-frequency = <100000>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_rtc_mc_8803>;
376 status = "okay";
377
378 rv8803@32 {
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "microcrystal,rv8803";
382 reg = <0x32>;
383 };
384
385 24c02@50 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "atmel,24c04";
389 reg = <0x50>;
390 };
391};
392
393&lpuart0 { /* console */
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_lpuart0>;
396 status = "okay";
397};