blob: bca3397d948e2b78d5c63e16a4bdf672aeee7673 [file] [log] [blame]
Gary Jennejohnffd0be32007-08-31 14:29:04 +02001/*
2 * (C) Copyright 2007
3 * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Gary Jennejohnffd0be32007-08-31 14:29:04 +02006 */
7/* sil680.c - ide support functions for the Sil0680A controller */
8
9/*
10 * The following parameters must be defined in the configuration file
11 * of the target board:
12 *
Jean-Christophe PLAGNIOL-VILLARD92dbcc32008-08-13 01:40:39 +020013 * #define CONFIG_IDE_SIL680
Gary Jennejohnffd0be32007-08-31 14:29:04 +020014 *
15 * #define CONFIG_PCI_PNP
16 * NOTE it may also be necessary to define this if the default of 8 is
17 * incorrect for the target board (e.g. the sequoia board requires 0).
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020018 * #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
Gary Jennejohnffd0be32007-08-31 14:29:04 +020019 *
Simon Glassb569a012017-05-17 03:25:30 -060020 * #define CONFIG_IDE
Gary Jennejohnffd0be32007-08-31 14:29:04 +020021 * #undef CONFIG_IDE_LED
22 * #undef CONFIG_IDE_RESET
23 * #define CONFIG_IDE_PREINIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020024 * #define CONFIG_SYS_IDE_MAXBUS 2 - modify to suit
25 * #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) - modify to suit
26 * #define CONFIG_SYS_ATA_BASE_ADDR 0
27 * #define CONFIG_SYS_ATA_IDE0_OFFSET 0
28 * #define CONFIG_SYS_ATA_IDE1_OFFSET 0
29 * #define CONFIG_SYS_ATA_DATA_OFFSET 0
30 * #define CONFIG_SYS_ATA_REG_OFFSET 0
31 * #define CONFIG_SYS_ATA_ALT_OFFSET 0x0004
Gary Jennejohnffd0be32007-08-31 14:29:04 +020032 *
33 * The mapping for PCI IO-space.
34 * NOTE this is the value for the sequoia board. Modify to suit.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035 * #define CONFIG_SYS_PCI0_IO_SPACE 0xE8000000
Gary Jennejohnffd0be32007-08-31 14:29:04 +020036 */
37
38#include <common.h>
Gary Jennejohnffd0be32007-08-31 14:29:04 +020039#include <ata.h>
40#include <ide.h>
41#include <pci.h>
42
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
Gary Jennejohnffd0be32007-08-31 14:29:04 +020044
45int ide_preinit (void)
46{
47 int status;
48 pci_dev_t devbusfn;
49 int l;
50
51 status = 1;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052 for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
Gary Jennejohnffd0be32007-08-31 14:29:04 +020053 ide_bus_offset[l] = -ATA_STATUS;
54 }
55 devbusfn = pci_find_device (0x1095, 0x0680, 0);
56 if (devbusfn != -1) {
57 status = 0;
58
59 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
60 (u32 *) &ide_bus_offset[0]);
61 ide_bus_offset[0] &= 0xfffffff8;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062 ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
Gary Jennejohnffd0be32007-08-31 14:29:04 +020063 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
64 (u32 *) &ide_bus_offset[1]);
65 ide_bus_offset[1] &= 0xfffffff8;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066 ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
Gary Jennejohnffd0be32007-08-31 14:29:04 +020067 /* init various things - taken from the Linux driver */
68 /* set PIO mode */
69 pci_write_config_byte(devbusfn, 0x80, 0x00);
70 pci_write_config_byte(devbusfn, 0x84, 0x00);
71 /* IDE0 */
72 pci_write_config_byte(devbusfn, 0xA1, 0x02);
73 pci_write_config_word(devbusfn, 0xA2, 0x328A);
74 pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
75 pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
76 pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
77 /* IDE1 */
78 pci_write_config_byte(devbusfn, 0xB1, 0x02);
79 pci_write_config_word(devbusfn, 0xB2, 0x328A);
80 pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
81 pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
82 pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
83 }
84 return (status);
85}
86
87void ide_set_reset (int flag) {
88 return;
89}