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git01.mediatek.com / filogic / uboot / 86a02eeed072532b08a07503da8d9838e87e6154 / . / arch / arm / dts / zynqmp-vpk120-revA.dts
blob: e0632883e4ece26c4e2440e642b7719d5fdc66a3 [file] [log] [blame]
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK120 RevA System Controller
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP System Controller on VPK120 board RevA";
21 compatible = "xlnx,zynqmp-vpk120-revA",
22 "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
23
24 aliases {
25 ethernet0 = &gem0;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 mmc0 = &sdhci0;
29 serial0 = &uart0;
30 serial1 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 nvmem0 = &eeprom;
35 };
36
37 chosen {
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49 autorepeat;
Michal Simek518d1662024-03-08 09:40:52 +0100[diff] [blame]50 button-16 {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]51 label = "sw16";
52 gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
53 linux,code = <BTN_MISC>;
54 wakeup-source;
55 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 heartbeat-led { /* ds40 */
62 label = "heartbeat";
63 gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]68 si5332_0: si5332-0 { /* ps_ref_clk */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <33333333>;
72 };
73
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]74 si5332_1: si5332-1 { /* clk0_sgmii */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <33333333>; /* FIXME */
78 };
79
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]80 si5332_2: si5332-2 { /* clk1_usb */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <27000000>;
84 };
85};
86
87&qspi { /* MIO 0-5 */
88 status = "okay";
89 flash@0 {
90 compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
91 #address-cells = <1>;
92 #size-cells = <1>;
93 reg = <0>;
94 spi-tx-bus-width = <4>;
95 spi-rx-bus-width = <4>;
96 spi-max-frequency = <108000000>;
97 partition@0 { /* for testing purpose */
98 label = "qspi";
99 reg = <0 0x4000000>;
100 };
101 };
102};
103
104&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
105 status = "okay";
106 non-removable;
107 disable-wp;
108 bus-width = <8>;
109 xlnx,mio-bank = <0>;
110};
111
112&uart0 { /* uart0 MIO38-39 */
113 status = "okay";
114 bootph-all;
115};
116
117&gem0 {
118 status = "okay";
119 phy-handle = <&phy0>;
120 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
121 is-internal-pcspma;
122 /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
Michal Simek3181a872023-10-12 14:58:47 +0200[diff] [blame]123 mdio: mdio {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
127 phy0: ethernet-phy@0 {
128 reg = <0>;
129 };
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]130 };
131};
132
133&gpio {
134 status = "okay";
135 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
136 "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
137 "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
138 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
139 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
140 "", "", "", "", "", /* 25 - 29 */
141 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
142 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
143 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
144 "", "", "", "", "", /* 45 - 49 */
145 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
146 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
147 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
148 "", "", "", "", "", /* 65 - 69 */
149 "", "", "", "", "", /* 70 - 74 */
150 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
151 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
152 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
153 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
154 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
155 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
156 "", "", "", "", "", /* 100 - 104 */
157 "", "", "", "", "", /* 105 - 109 */
158 "", "", "", "", "", /* 110 - 114 */
159 "", "", "", "", "", /* 115 - 119 */
160 "", "", "", "", "", /* 120 - 124 */
161 "", "", "", "", "", /* 125 - 129 */
162 "", "", "", "", "", /* 130 - 134 */
163 "", "", "", "", "", /* 135 - 139 */
164 "", "", "", "", "", /* 140 - 144 */
165 "", "", "", "", "", /* 145 - 149 */
166 "", "", "", "", "", /* 150 - 154 */
167 "", "", "", "", "", /* 155 - 159 */
168 "", "", "", "", "", /* 160 - 164 */
169 "", "", "", "", "", /* 165 - 169 */
170 "", "", "", ""; /* 170 - 173 */
171};
172
173&i2c0 { /* MIO 34-35 - can't stay here */
174 status = "okay";
175 clock-frequency = <400000>;
176 pinctrl-names = "default", "gpio";
177 pinctrl-0 = <&pinctrl_i2c0_default>;
178 pinctrl-1 = <&pinctrl_i2c0_gpio>;
179 scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
180 sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
181
182 tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
183 compatible = "ti,tca6416";
184 reg = <0x20>;
185 gpio-controller; /* interrupt not connected */
186 #gpio-cells = <2>;
187 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */
188 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
189 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
190 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
191 };
192
193 i2c-mux@74 { /* u33 */
194 compatible = "nxp,pca9548";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 reg = <0x74>;
198 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
199 pmbus_i2c: i2c@0 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0>;
203 /* On connector J325 */
204 ir38060_41: regulator@41 { /* IR38060 - u259 */
205 compatible = "infineon,ir38060", "infineon,ir38064";
206 reg = <0x41>; /* i2c addr 0x11 */
207 };
208 ir38164_43: regulator@43 { /* IR38164 - u13 */
209 compatible = "infineon,ir38164";
210 reg = <0x43>; /* i2c addr 0x13 */
211 };
212 ir35221_45: pmic@46 { /* IR35221 - u152 */
213 compatible = "infineon,ir35221";
214 reg = <0x46>; /* PMBUS - 0x16 */
215 };
216 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
217 compatible = "infineon,irps5401";
218 reg = <0x47>; /* i2c addr 0x17 */
219 };
220 ir38164_49: regulator@49 { /* IR38164 - u189 */
221 compatible = "infineon,ir38164";
222 reg = <0x49>; /* i2c addr 0x19 */
223 };
224 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
225 compatible = "infineon,irps5401";
226 reg = <0x4c>; /* i2c addr 0x1c */
227 };
228 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
229 compatible = "infineon,irps5401";
230 reg = <0x4d>; /* i2c addr 0x1c */
231 };
232 ir38164_4e: regulator@4e { /* IR38164 - u184 */
233 compatible = "infineon,ir38164";
234 reg = <0x4e>; /* i2c addr 0x1e */
235 };
236 ir38164_4f: regulator@4f { /* IR38164 - u187 */
237 compatible = "infineon,ir38164";
238 reg = <0x4f>; /* i2c addr 0x1f */
239 };
240 };
241 pmbus1_ina226_i2c: i2c@1 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <1>;
245 /* FIXME check alerts coming to SC */
246 vccint: ina226@40 { /* u65 */
247 compatible = "ti,ina226";
248 reg = <0x40>;
249 shunt-resistor = <5000>;
250 };
251 vcc_soc: ina226@41 { /* u161 */
252 compatible = "ti,ina226";
253 reg = <0x41>;
254 shunt-resistor = <5000>;
255 };
256 vcc_pmc: ina226@42 { /* u163 */
257 compatible = "ti,ina226";
258 reg = <0x42>;
259 shunt-resistor = <5000>;
260 };
261 vcc_ram: ina226@43 { /* u5 */
262 compatible = "ti,ina226";
263 reg = <0x43>;
264 shunt-resistor = <5000>;
265 };
266 vcc_pslp: ina226@44 { /* u165 */
267 compatible = "ti,ina226";
268 reg = <0x44>;
269 shunt-resistor = <5000>;
270 };
271 vcc_psfp: ina226@45 { /* u164 */
272 compatible = "ti,ina226";
273 reg = <0x45>;
274 shunt-resistor = <5000>;
275 };
276 };
277 i2c@2 { /* NC */ /* FIXME maybe remove */
278 #address-cells = <1>;
279 #size-cells = <0>;
280 reg = <2>;
281 };
282 pmbus2_ina226_i2c: i2c@3 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 reg = <3>;
286 /* FIXME check alerts coming to SC */
287 vccaux: ina226@40 { /* u166 */
288 compatible = "ti,ina226";
289 reg = <0x40>;
290 shunt-resistor = <5000>;
291 };
292 vccaux_pmc: ina226@41 { /* u168 */
293 compatible = "ti,ina226";
294 reg = <0x41>;
295 shunt-resistor = <5000>;
296 };
297 mgtavcc: ina226@42 { /* u265 */
298 compatible = "ti,ina226";
299 reg = <0x42>;
300 shunt-resistor = <5000>;
301 };
302 vcc1v5: ina226@43 { /* u264 */
303 compatible = "ti,ina226";
304 reg = <0x43>;
305 shunt-resistor = <5000>;
306 };
307 vcco_mio: ina226@45 { /* u172 */
308 compatible = "ti,ina226";
309 reg = <0x45>;
310 shunt-resistor = <5000>;
311 };
312 mgtavtt: ina226@46 { /* u188 */
313 compatible = "ti,ina226";
314 reg = <0x46>;
315 shunt-resistor = <2000>;
316 };
317 vcco_502: ina226@47 { /* u174 */
318 compatible = "ti,ina226";
319 reg = <0x47>;
320 shunt-resistor = <5000>;
321 };
322 mgtvccaux: ina226@48 { /* u176 */
323 compatible = "ti,ina226";
324 reg = <0x48>;
325 shunt-resistor = <5000>;
326 };
327 vcc1v1_lp4: ina226@49 { /* u186 */
328 compatible = "ti,ina226";
329 reg = <0x49>;
330 shunt-resistor = <2000>;
331 };
332 vadj_fmc: ina226@4a { /* u184 */
333 compatible = "ti,ina226";
334 reg = <0x4a>;
335 shunt-resistor = <2000>;
336 };
337 lpdmgtyavcc: ina226@4b { /* u177 */
338 compatible = "ti,ina226";
339 reg = <0x4b>;
340 shunt-resistor = <5000>;
341 };
342 lpdmgtyavtt: ina226@4c { /* u260 */
343 compatible = "ti,ina226";
344 reg = <0x4c>;
345 shunt-resistor = <2000>;
346 };
347 lpdmgtyvccaux: ina226@4d { /* u234 */
348 compatible = "ti,ina226";
349 reg = <0x4d>;
350 shunt-resistor = <5000>;
351 };
352 };
353 i2c@4 { /* NC */
354 #address-cells = <1>;
355 #size-cells = <0>;
356 reg = <4>;
357 };
358 i2c@5 { /* NC */
359 #address-cells = <1>;
360 #size-cells = <0>;
361 reg = <5>;
362 };
363 user_si570: i2c@6 {
364 #address-cells = <1>;
365 #size-cells = <0>;
366 reg = <6>;
367 user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
368 #clock-cells = <0>;
369 compatible = "silabs,si570";
370 reg = <0x5f>;
371 temperature-stability = <50>;
372 factory-fout = <100000000>;
373 clock-frequency = <100000000>;
374 clock-output-names = "fmc_si570";
375 };
376
377 };
378 /* 7 unused */
379 };
380};
381
382&i2c1 { /* i2c1 MIO 36-37 */
383 status = "okay";
384 clock-frequency = <400000>;
385 pinctrl-names = "default", "gpio";
386 pinctrl-0 = <&pinctrl_i2c1_default>;
387 pinctrl-1 = <&pinctrl_i2c1_gpio>;
388 scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
389 sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
390
391 i2c-mux@74 { /* u35 */
392 compatible = "nxp,pca9548";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 reg = <0x74>;
396 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
397 ref_clk_i2c: i2c@0 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 reg = <0>;
401 /* Use for storing information about SC board */
402 eeprom: eeprom@54 { /* u34 - m24128 16kB */
403 compatible = "st,24c128", "atmel,24c128";
404 reg = <0x54>; /* & 0x5c */
405 };
406 ref_clk: clock-generator@5d { /* u32 */
407 #clock-cells = <0>;
408 compatible = "silabs,si570";
409 reg = <0x5d>;
410 temperature-stability = <50>;
411 factory-fout = <33333333>;
412 clock-frequency = <33333333>;
413 clock-output-names = "ref_clk";
414 silabs,skip-recall;
415 };
416 };
417 fmcp1_i2c: i2c@1 {
418 #address-cells = <1>;
419 #size-cells = <0>;
420 reg = <1>;
421 /* FIXME connection to Samtec J51C */
422 /* expected eeprom 0x50 SE cards */
423 };
424 i2c@2 { /* NC - FIXME */
425 #address-cells = <1>;
426 #size-cells = <0>;
427 reg = <2>;
428 };
429 lpddr4_si570_clk3_i2c: i2c@3 {
430 #address-cells = <1>;
431 #size-cells = <0>;
432 reg = <3>;
433 lpddr4_clk3: clock-generator@60 { /* u4 */
434 #clock-cells = <0>;
435 compatible = "silabs,si570";
436 reg = <0x60>;
437 temperature-stability = <50>;
438 factory-fout = <200000000>;
439 clock-frequency = <200000000>;
440 clock-output-names = "lpddr4_clk3";
441 };
442 };
443 lpddr4_si570_clk2_i2c: i2c@4 {
444 #address-cells = <1>;
445 #size-cells = <0>;
446 reg = <4>;
447 lpddr4_clk2: clock-generator@60 { /* u3 */
448 #clock-cells = <0>;
449 compatible = "silabs,si570";
450 reg = <0x60>;
451 temperature-stability = <50>;
452 factory-fout = <200000000>;
453 clock-frequency = <200000000>;
454 clock-output-names = "lpddr4_clk2";
455 };
456 };
457 lpddr4_si570_clk1_i2c: i2c@5 {
458 #address-cells = <1>;
459 #size-cells = <0>;
460 reg = <5>;
461 lpddr4_clk1: clock-generator@60 { /* u248 */
462 #clock-cells = <0>;
463 compatible = "silabs,si570";
464 reg = <0x60>;
465 temperature-stability = <50>;
466 factory-fout = <200000000>;
467 clock-frequency = <200000000>;
468 clock-output-names = "lpddr4_clk1";
469 };
470 };
471 qsfpdd_i2c: i2c@6 {
472 #address-cells = <1>;
473 #size-cells = <0>;
474 reg = <6>;
475 /* J1/J2 connectors */
476 };
477 idt8a34001_i2c: i2c@7 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 reg = <7>;
481 /* Via J310 connector */
482 idt_8a34001: phc@5b {
483 compatible = "idt,8a34001"; /* u219B */
484 reg = <0x5b>; /* FIXME not in schematics */
485 };
486 };
487 };
488};
489
490&usb0 { /* MIO52 - MIO63 */
491 status = "okay";
492 phy-names = "usb3-phy";
493 phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
494};
495
496&psgtr {
497 status = "okay";
498 /* sgmii, usb3 */
499 clocks = <&si5332_1>, <&si5332_2>;
500 clock-names = "ref0", "ref1";
501};
502
503&dwc3_0 {
504 status = "okay";
505 dr_mode = "peripheral";
506 snps,dis_u2_susphy_quirk;
507 snps,dis_u3_susphy_quirk;
508 maximum-speed = "super-speed";
509};
510
511&xilinx_ams {
512 status = "okay";
513};
514
515&ams_ps {
516 status = "okay";
517};
518
519&ams_pl {
520 status = "okay";
521};
522
523&pinctrl0 {
524 status = "okay";
525 pinctrl_i2c0_default: i2c0-default {
526 mux {
527 groups = "i2c0_8_grp";
528 function = "i2c0";
529 };
530
531 conf {
532 groups = "i2c0_8_grp";
533 bias-pull-up;
534 slew-rate = <SLEW_RATE_SLOW>;
535 power-source = <IO_STANDARD_LVCMOS18>;
536 };
537 };
538
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame]539 pinctrl_i2c0_gpio: i2c0-gpio-grp {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]540 mux {
541 groups = "gpio0_34_grp", "gpio0_35_grp";
542 function = "gpio0";
543 };
544
545 conf {
546 groups = "gpio0_34_grp", "gpio0_35_grp";
547 slew-rate = <SLEW_RATE_SLOW>;
548 power-source = <IO_STANDARD_LVCMOS18>;
549 };
550 };
551
552 pinctrl_i2c1_default: i2c1-default {
553 mux {
554 groups = "i2c1_9_grp";
555 function = "i2c1";
556 };
557
558 conf {
559 groups = "i2c1_9_grp";
560 bias-pull-up;
561 slew-rate = <SLEW_RATE_SLOW>;
562 power-source = <IO_STANDARD_LVCMOS18>;
563 };
564 };
565
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame]566 pinctrl_i2c1_gpio: i2c1-gpio-grp {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]567 mux {
568 groups = "gpio0_36_grp", "gpio0_37_grp";
569 function = "gpio0";
570 };
571
572 conf {
573 groups = "gpio0_36_grp", "gpio0_37_grp";
574 slew-rate = <SLEW_RATE_SLOW>;
575 power-source = <IO_STANDARD_LVCMOS18>;
576 };
577 };
578};