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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ying Zhangded0f0f2013-08-16 15:16:13 +08002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Ying Zhangded0f0f2013-08-16 15:16:13 +08004 */
5
6#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -07007#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -07008#include <hang.h>
Ying Zhangded0f0f2013-08-16 15:16:13 +08009#include <spi_flash.h>
10#include <malloc.h>
11
12#define ESPI_BOOT_IMAGE_SIZE 0x48
13#define ESPI_BOOT_IMAGE_ADDR 0x50
Tom Rini364d0022023-01-10 11:19:45 -050014#define CFG_CFG_DATA_SECTOR 0
Ying Zhangded0f0f2013-08-16 15:16:13 +080015
Simon Glassdd8e2242016-09-24 18:20:10 -060016void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
Prabhakar Kushwaha9ea255a2014-04-08 19:13:22 +053017{
18 struct spi_flash *flash;
19
20 flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
21 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
22 if (flash == NULL) {
23 puts("\nspi_flash_probe failed");
24 hang();
25 }
26
27 spi_flash_read(flash, offs, size, vdst);
28}
29
Ying Zhangded0f0f2013-08-16 15:16:13 +080030/*
31 * The main entry for SPI booting. It's necessary that SDRAM is already
32 * configured and available since this code loads the main U-Boot image
33 * from SPI into SDRAM and starts it from there.
34 */
Simon Glassdd8e2242016-09-24 18:20:10 -060035void fsl_spi_boot(void)
Ying Zhangded0f0f2013-08-16 15:16:13 +080036{
37 void (*uboot)(void) __noreturn;
Prabhakar Kushwaha77aa1322014-04-08 19:13:11 +053038 u32 offset, code_len, copy_len = 0;
39#ifndef CONFIG_FSL_CORENET
Ying Zhangded0f0f2013-08-16 15:16:13 +080040 unsigned char *buf = NULL;
Prabhakar Kushwaha77aa1322014-04-08 19:13:11 +053041#endif
Ying Zhangded0f0f2013-08-16 15:16:13 +080042 struct spi_flash *flash;
43
44 flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
45 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
46 if (flash == NULL) {
47 puts("\nspi_flash_probe failed");
48 hang();
49 }
50
Priyanka Jainfed1d312013-11-28 10:08:12 +053051#ifdef CONFIG_FSL_CORENET
Tom Rini6a5dccc2022-11-16 13:10:41 -050052 offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
53 code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE;
Priyanka Jainfed1d312013-11-28 10:08:12 +053054#else
Ying Zhangded0f0f2013-08-16 15:16:13 +080055 /*
56 * Load U-Boot image from SPI flash into RAM
57 */
58 buf = malloc(flash->page_size);
59 if (buf == NULL) {
60 puts("\nmalloc failed");
61 hang();
62 }
63 memset(buf, 0, flash->page_size);
64
Tom Rini364d0022023-01-10 11:19:45 -050065 spi_flash_read(flash, CFG_CFG_DATA_SECTOR,
Ying Zhangded0f0f2013-08-16 15:16:13 +080066 flash->page_size, (void *)buf);
67 offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
68 /* Skip spl code */
Tom Rini6a5dccc2022-11-16 13:10:41 -050069 offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
Ying Zhangded0f0f2013-08-16 15:16:13 +080070 /* Get the code size from offset 0x48 */
71 code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
72 /* Skip spl code */
73 code_len = code_len - CONFIG_SPL_MAX_SIZE;
Priyanka Jainfed1d312013-11-28 10:08:12 +053074#endif
Ying Zhangded0f0f2013-08-16 15:16:13 +080075 /* copy code to DDR */
Prabhakar Kushwaha77aa1322014-04-08 19:13:11 +053076 printf("Loading second stage boot loader ");
77 while (copy_len <= code_len) {
78 spi_flash_read(flash, offset + copy_len, 0x2000,
Tom Rini6a5dccc2022-11-16 13:10:41 -050079 (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST
Prabhakar Kushwaha77aa1322014-04-08 19:13:11 +053080 + copy_len));
81 copy_len = copy_len + 0x2000;
82 putc('.');
83 }
84
Ying Zhangded0f0f2013-08-16 15:16:13 +080085 /*
86 * Jump to U-Boot image
87 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050088 flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
89 uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START;
Ying Zhangded0f0f2013-08-16 15:16:13 +080090 (*uboot)();
91}