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git01.mediatek.com / filogic / uboot / 8699b2e8645ac01da51a8f159ad9478c2a2452e1 / . / drivers / net / dwmac_meson8b.c
blob: c0b6ef499422cb4360356aad1df46aed76b8ed67 [file] [log] [blame]
Neil Armstrong145aff72021-02-24 20:33:56 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2021 BayLibre, SAS
4 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <dm.h>
9#include <phy.h>
10#include "designware.h"
11#include <dm/device_compat.h>
12#include <linux/err.h>
13
14#define ETH_REG_0 0x0
15#define ETH_REG_1 0x4
16#define ETH_REG_2 0x18
17#define ETH_REG_3 0x1c
18
19#define GX_ETH_REG_0_PHY_INTF BIT(0)
20#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
21#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
22#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
23#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
24#define GX_ETH_REG_0_CLK_EN BIT(12)
25
26#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
27#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
28#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
29#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
30#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
31#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
32#define AXG_ETH_REG_0_CLK_EN BIT(12)
33
34struct dwmac_meson8b_plat {
35 struct dw_eth_pdata dw_eth_pdata;
36 int (*dwmac_setup)(struct udevice *dev, struct eth_pdata *edata);
37 void *regs;
38};
39
40static int dwmac_meson8b_of_to_plat(struct udevice *dev)
41{
42 struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
43
44 pdata->regs = (void *)dev_read_addr_index(dev, 1);
45 if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE)
46 return -EINVAL;
47
48 pdata->dwmac_setup = (void *)dev_get_driver_data(dev);
49 if (!pdata->dwmac_setup)
50 return -EINVAL;
51
52 return designware_eth_of_to_plat(dev);
53}
54
55static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata)
56{
57 struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
58
59 switch (edata->phy_interface) {
60 case PHY_INTERFACE_MODE_RGMII:
61 case PHY_INTERFACE_MODE_RGMII_ID:
62 case PHY_INTERFACE_MODE_RGMII_RXID:
63 case PHY_INTERFACE_MODE_RGMII_TXID:
64 /* Set RGMII mode */
65 setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
66 AXG_ETH_REG_0_TX_PHASE(1) |
67 AXG_ETH_REG_0_TX_RATIO(4) |
68 AXG_ETH_REG_0_PHY_CLK_EN |
69 AXG_ETH_REG_0_CLK_EN);
70 break;
71
72 case PHY_INTERFACE_MODE_RMII:
73 /* Set RMII mode */
74 out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
75 AXG_ETH_REG_0_INVERT_RMII_CLK |
76 AXG_ETH_REG_0_CLK_EN);
77 break;
78 default:
79 dev_err(dev, "Unsupported PHY mode\n");
80 return -EINVAL;
81 }
82
83 return 0;
84}
85
86static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata)
87{
88 struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
89
90 switch (edata->phy_interface) {
91 case PHY_INTERFACE_MODE_RGMII:
92 case PHY_INTERFACE_MODE_RGMII_ID:
93 case PHY_INTERFACE_MODE_RGMII_RXID:
94 case PHY_INTERFACE_MODE_RGMII_TXID:
95 /* Set RGMII mode */
96 setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
97 GX_ETH_REG_0_TX_PHASE(1) |
98 GX_ETH_REG_0_TX_RATIO(4) |
99 GX_ETH_REG_0_PHY_CLK_EN |
100 GX_ETH_REG_0_CLK_EN);
101
102 break;
103
104 case PHY_INTERFACE_MODE_RMII:
105 /* Set RMII mode */
106 out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
107 GX_ETH_REG_0_CLK_EN);
108
109 if (!IS_ENABLED(CONFIG_MESON_GXBB))
110 writel(0x10110181, plat->regs + ETH_REG_2);
111
112 break;
113 default:
114 dev_err(dev, "Unsupported PHY mode\n");
115 return -EINVAL;
116 }
117
118 return 0;
119}
120
121static int dwmac_meson8b_probe(struct udevice *dev)
122{
123 struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
124 struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
125 int ret;
126
127 ret = pdata->dwmac_setup(dev, edata);
128 if (ret)
129 return ret;
130
131 return designware_eth_probe(dev);
132}
133
134static const struct udevice_id dwmac_meson8b_ids[] = {
135 { .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx },
136 { .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg },
137 { }
138};
139
140U_BOOT_DRIVER(dwmac_meson8b) = {
141 .name = "dwmac_meson8b",
142 .id = UCLASS_ETH,
143 .of_match = dwmac_meson8b_ids,
144 .of_to_plat = dwmac_meson8b_of_to_plat,
145 .probe = dwmac_meson8b_probe,
146 .ops = &designware_eth_ops,
147 .priv_auto = sizeof(struct dw_eth_dev),
148 .plat_auto = sizeof(struct dwmac_meson8b_plat),
149 .flags = DM_FLAG_ALLOC_PRIV_DMA,
150};