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Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +09001/*
2 * include/configs/alt.h
3 * This file is alt board configuration.
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __ALT_H
11#define __ALT_H
12
13#undef DEBUG
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090014#define CONFIG_R8A7794
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090015#define CONFIG_RMOBILE_BOARD_STRING "Alt"
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090016
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090017#include "rcar-gen2-common.h"
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090018
Nobuhiro Iwamatsua341e772014-10-31 16:16:28 +090019#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
20#define CONFIG_SYS_TEXT_BASE 0x70000000
21#else
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090022#define CONFIG_SYS_TEXT_BASE 0xE6304000
Nobuhiro Iwamatsua341e772014-10-31 16:16:28 +090023#endif
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090024
Nobuhiro Iwamatsua341e772014-10-31 16:16:28 +090025#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
26#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
27#else
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090028#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
Nobuhiro Iwamatsua341e772014-10-31 16:16:28 +090029#endif
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090030#define STACK_AREA_SIZE 0xC000
31#define LOW_LEVEL_MERAM_STACK \
32 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
33
34/* MEMORY */
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090035#define RCAR_GEN2_SDRAM_BASE 0x40000000
36#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
37#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090038
39/* SCIF */
40#define CONFIG_SCIF_CONSOLE
41#define CONFIG_CONS_SCIF2
Nobuhiro Iwamatsuc0db2e82014-11-10 14:43:59 +090042#define CONFIG_SCIF_USE_EXT_CLK
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090043
44/* FLASH */
45#define CONFIG_SPI
46#define CONFIG_SPI_FLASH_BAR
47#define CONFIG_SH_QSPI
48#define CONFIG_SPI_FLASH
49#define CONFIG_SPI_FLASH_SPANSION
50#define CONFIG_SPI_FLASH_QUAD
51#define CONFIG_SYS_NO_FLASH
52
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090053/* SH Ether */
54#define CONFIG_NET_MULTI
55#define CONFIG_SH_ETHER
56#define CONFIG_SH_ETHER_USE_PORT 0
57#define CONFIG_SH_ETHER_PHY_ADDR 0x1
58#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
59#define CONFIG_SH_ETHER_CACHE_WRITEBACK
60#define CONFIG_SH_ETHER_CACHE_INVALIDATE
61#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
62#define CONFIG_PHYLIB
63#define CONFIG_PHY_MICREL
64#define CONFIG_BITBANGMII
65#define CONFIG_BITBANGMII_MULTI
66
67/* Board Clock */
68#define RMOBILE_XTAL_CLK 20000000u
69#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
70#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
71#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
72#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
Nobuhiro Iwamatsuc0db2e82014-11-10 14:43:59 +090073#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090074
75#define CONFIG_SYS_TMU_CLK_DIV 4
76
77/* i2c */
78#define CONFIG_CMD_I2C
79#define CONFIG_SYS_I2C
80#define CONFIG_SYS_I2C_SH
81#define CONFIG_SYS_I2C_SLAVE 0x7F
82#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090083#define CONFIG_SYS_I2C_SH_SPEED0 400000
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090084#define CONFIG_SYS_I2C_SH_SPEED1 400000
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +090085#define CONFIG_SYS_I2C_SH_SPEED2 400000
86#define CONFIG_SH_I2C_DATA_HIGH 4
87#define CONFIG_SH_I2C_DATA_LOW 5
88#define CONFIG_SH_I2C_CLOCK 10000000
89
90#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
91
Nobuhiro Iwamatsu8208d9b2014-10-31 16:30:26 +090092/* USB */
93#define CONFIG_USB_STORAGE
94#define CONFIG_USB_EHCI
95#define CONFIG_USB_EHCI_RMOBILE
96#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
97
Nobuhiro Iwamatsu86690f52014-12-03 15:30:30 +090098/* MMCIF */
99#define CONFIG_MMC
100#define CONFIG_GENERIC_MMC
101#define CONFIG_CMD_MMC
102
103#define CONFIG_SH_MMCIF
104#define CONFIG_SH_MMCIF_ADDR 0xee200000
105#define CONFIG_SH_MMCIF_CLK 48000000
106
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +0900107/* Module stop status bits */
108/* INTC-RT */
109#define CONFIG_SMSTP0_ENA 0x00400000
110/* MSIF */
111#define CONFIG_SMSTP2_ENA 0x00002000
112/* INTC-SYS, IRQC */
113#define CONFIG_SMSTP4_ENA 0x00000180
114/* SCIF2 */
115#define CONFIG_SMSTP7_ENA 0x00080000
116
Nobuhiro Iwamatsuddbf3032014-06-26 10:23:30 +0900117#endif /* __ALT_H */