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git01.mediatek.com / filogic / uboot / 85d018f70bab23924fa83c38dcf4346973fee3e9 / . / arch / arm / dts / imx8mm-verdin-wifi-dev-u-boot.dtsi
blob: 90183aff8bcc8ba1a7a64aa2beb74833849ecd7d [file] [log] [blame]
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2020-2022 Toradex
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
Emanuele Ghidoliff939c22024-02-23 10:11:40 +0100[diff] [blame]9 aliases {
10 eeprom0 = &eeprom_module;
11 eeprom1 = &eeprom_carrier_board;
12 eeprom2 = &eeprom_display_adapter;
13 };
14
Emanuele Ghidoli26b5cba2024-02-23 10:11:41 +0100[diff] [blame]15 sysinfo {
16 compatible = "toradex,sysinfo";
17 };
18
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]19 wdt-reboot {
20 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]22 wdt = <&wdog1>;
23 };
24};
25
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]26&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]28};
29
30&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]32};
33
Marcel Ziswiler8d322832023-08-23 00:17:25 +0200[diff] [blame]34&aips4 {
35 bootph-pre-ram;
36};
37
Marek Vasutf44c7382024-04-26 01:00:37 +0200[diff] [blame]38&binman {
39 section {
40 fit {
41 offset = <0x5fc00>;
42 };
43 };
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]44};
45
46&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]48};
49
50&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]52};
53
54&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]56};
57
58&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]60};
61
62&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]64
65 ctrl-sleep-moci-hog {
66 bootph-pre-ram;
Stefan Eichenberger11e22d32024-04-17 10:49:02 +0200[diff] [blame]67 gpio-hog;
68 output-high;
69 gpios = <1 GPIO_ACTIVE_HIGH>;
70 line-name = "CTRL_SLEEP_MOCI#";
71
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]72 };
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]73};
74
75&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]77
78 eeprom_module: eeprom@50 {
79 compatible = "i2c-eeprom";
80 pagesize = <16>;
81 reg = <0x50>;
82 };
83};
84
85&i2c2 {
86 status = "okay";
87};
88
89&i2c4 {
90 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
91 eeprom_display_adapter: eeprom@50 {
92 compatible = "i2c-eeprom";
93 pagesize = <16>;
94 reg = <0x50>;
95 };
96
97 /* EEPROM on carrier board */
98 eeprom_carrier_board: eeprom@57 {
99 compatible = "i2c-eeprom";
100 pagesize = <16>;
101 reg = <0x57>;
102 };
103};
104
Andrejs Cainikovs5ab25a12023-07-11 11:09:16 +0200[diff] [blame]105&pinctrl_ctrl_sleep_moci {
106 bootph-pre-ram;
107};
108
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]109&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]111};
112
113&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]115};
116
117&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]119};
120
121&pinctrl_usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]123};
124
125&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]127};
128
129&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]131};
132
133&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]134 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]135};
136
Marcel Ziswiler8d322832023-08-23 00:17:25 +0200[diff] [blame]137&usbmisc1 {
138 bootph-pre-ram;
139};
140
141/* Verdin USB_1 */
142&usbotg1 {
143 bootph-pre-ram;
144};
145
146&usbphynop1 {
147 bootph-pre-ram;
148};
149
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]150&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]151 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]152};
153
154&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]155 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]156};
157
158&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]159 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]160};
161
162&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]163 bootph-pre-ram;
Marcel Ziswiler2712c782022-07-21 15:41:23 +0200[diff] [blame]164};