Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Philipp Tomsich | fcc1d63 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 2 | /* |
| 3 | * eFuse driver for Rockchip devices |
| 4 | * |
| 5 | * Copyright 2017, Theobroma Systems Design und Consulting GmbH |
| 6 | * Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
Philipp Tomsich | fcc1d63 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <command.h> |
| 12 | #include <display_options.h> |
| 13 | #include <dm.h> |
| 14 | #include <linux/bitops.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <misc.h> |
| 17 | |
| 18 | #define RK3399_A_SHIFT 16 |
| 19 | #define RK3399_A_MASK 0x3ff |
| 20 | #define RK3399_NFUSES 32 |
| 21 | #define RK3399_BYTES_PER_FUSE 4 |
| 22 | #define RK3399_STROBSFTSEL BIT(9) |
| 23 | #define RK3399_RSB BIT(7) |
| 24 | #define RK3399_PD BIT(5) |
| 25 | #define RK3399_PGENB BIT(3) |
| 26 | #define RK3399_LOAD BIT(2) |
| 27 | #define RK3399_STROBE BIT(1) |
| 28 | #define RK3399_CSB BIT(0) |
| 29 | |
| 30 | struct rockchip_efuse_regs { |
| 31 | u32 ctrl; /* 0x00 efuse control register */ |
| 32 | u32 dout; /* 0x04 efuse data out register */ |
| 33 | u32 rf; /* 0x08 efuse redundancy bit used register */ |
| 34 | u32 _rsvd0; |
| 35 | u32 jtag_pass; /* 0x10 JTAG password */ |
| 36 | u32 strobe_finish_ctrl; |
| 37 | /* 0x14 efuse strobe finish control register */ |
| 38 | }; |
| 39 | |
| 40 | struct rockchip_efuse_platdata { |
| 41 | void __iomem *base; |
| 42 | struct clk *clk; |
| 43 | }; |
| 44 | |
| 45 | #if defined(DEBUG) |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 46 | static int dump_efuses(struct cmd_tbl *cmdtp, int flag, |
| 47 | int argc, char *const argv[]) |
Philipp Tomsich | fcc1d63 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 48 | { |
| 49 | /* |
| 50 | * N.B.: This function is tailored towards the RK3399 and assumes that |
| 51 | * there's always 32 fuses x 32 bits (i.e. 128 bytes of data) to |
| 52 | * be read. |
| 53 | */ |
| 54 | |
| 55 | struct udevice *dev; |
| 56 | u8 fuses[128]; |
| 57 | int ret; |
| 58 | |
| 59 | /* retrieve the device */ |
| 60 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
| 61 | DM_GET_DRIVER(rockchip_efuse), &dev); |
| 62 | if (ret) { |
| 63 | printf("%s: no misc-device found\n", __func__); |
| 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | ret = misc_read(dev, 0, &fuses, sizeof(fuses)); |
Simon Glass | 587dc40 | 2018-11-06 15:21:39 -0700 | [diff] [blame] | 68 | if (ret < 0) { |
Philipp Tomsich | fcc1d63 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 69 | printf("%s: misc_read failed\n", __func__); |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | printf("efuse-contents:\n"); |
| 74 | print_buffer(0, fuses, 1, 128, 16); |
| 75 | |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | U_BOOT_CMD( |
| 80 | rk3399_dump_efuses, 1, 1, dump_efuses, |
| 81 | "Dump the content of the efuses", |
| 82 | "" |
| 83 | ); |
| 84 | #endif |
| 85 | |
| 86 | static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset, |
| 87 | void *buf, int size) |
| 88 | { |
| 89 | struct rockchip_efuse_platdata *plat = dev_get_platdata(dev); |
| 90 | struct rockchip_efuse_regs *efuse = |
| 91 | (struct rockchip_efuse_regs *)plat->base; |
| 92 | |
| 93 | unsigned int addr_start, addr_end, addr_offset; |
| 94 | u32 out_value; |
| 95 | u8 bytes[RK3399_NFUSES * RK3399_BYTES_PER_FUSE]; |
| 96 | int i = 0; |
| 97 | u32 addr; |
| 98 | |
| 99 | addr_start = offset / RK3399_BYTES_PER_FUSE; |
| 100 | addr_offset = offset % RK3399_BYTES_PER_FUSE; |
| 101 | addr_end = DIV_ROUND_UP(offset + size, RK3399_BYTES_PER_FUSE); |
| 102 | |
| 103 | /* cap to the size of the efuse block */ |
| 104 | if (addr_end > RK3399_NFUSES) |
| 105 | addr_end = RK3399_NFUSES; |
| 106 | |
| 107 | writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, |
| 108 | &efuse->ctrl); |
| 109 | udelay(1); |
| 110 | for (addr = addr_start; addr < addr_end; addr++) { |
| 111 | setbits_le32(&efuse->ctrl, |
| 112 | RK3399_STROBE | (addr << RK3399_A_SHIFT)); |
| 113 | udelay(1); |
| 114 | out_value = readl(&efuse->dout); |
| 115 | clrbits_le32(&efuse->ctrl, RK3399_STROBE); |
| 116 | udelay(1); |
| 117 | |
| 118 | memcpy(&bytes[i], &out_value, RK3399_BYTES_PER_FUSE); |
| 119 | i += RK3399_BYTES_PER_FUSE; |
| 120 | } |
| 121 | |
| 122 | /* Switch to standby mode */ |
| 123 | writel(RK3399_PD | RK3399_CSB, &efuse->ctrl); |
| 124 | |
| 125 | memcpy(buf, bytes + addr_offset, size); |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | static int rockchip_efuse_read(struct udevice *dev, int offset, |
| 131 | void *buf, int size) |
| 132 | { |
| 133 | return rockchip_rk3399_efuse_read(dev, offset, buf, size); |
| 134 | } |
| 135 | |
| 136 | static const struct misc_ops rockchip_efuse_ops = { |
| 137 | .read = rockchip_efuse_read, |
| 138 | }; |
| 139 | |
| 140 | static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev) |
| 141 | { |
| 142 | struct rockchip_efuse_platdata *plat = dev_get_platdata(dev); |
| 143 | |
Philipp Tomsich | 3b50596 | 2017-09-12 17:32:26 +0200 | [diff] [blame] | 144 | plat->base = dev_read_addr_ptr(dev); |
Philipp Tomsich | fcc1d63 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | static const struct udevice_id rockchip_efuse_ids[] = { |
| 149 | { .compatible = "rockchip,rk3399-efuse" }, |
| 150 | {} |
| 151 | }; |
| 152 | |
| 153 | U_BOOT_DRIVER(rockchip_efuse) = { |
| 154 | .name = "rockchip_efuse", |
| 155 | .id = UCLASS_MISC, |
| 156 | .of_match = rockchip_efuse_ids, |
| 157 | .ofdata_to_platdata = rockchip_efuse_ofdata_to_platdata, |
| 158 | .platdata_auto_alloc_size = sizeof(struct rockchip_efuse_platdata), |
| 159 | .ops = &rockchip_efuse_ops, |
| 160 | }; |