Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * U-boot - Configuration file for BF561 EZKIT board |
| 3 | */ |
| 4 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 5 | #ifndef __CONFIG_BF561_EZKIT_H__ |
| 6 | #define __CONFIG_BF561_EZKIT_H__ |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 7 | |
Mike Frysinger | 18a407c | 2009-04-24 17:22:40 -0400 | [diff] [blame] | 8 | #include <asm/config-pre.h> |
Mike Frysinger | f0dd792 | 2008-02-18 05:26:48 -0500 | [diff] [blame] | 9 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 10 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 11 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 12 | * Processor Settings |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 13 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 14 | #define CONFIG_BFIN_CPU bf561-0.3 |
| 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 16 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 17 | |
| 18 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 19 | * Clock Settings |
| 20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
| 21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 22 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 24 | #define CONFIG_CLKIN_HZ 30000000 |
| 25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
| 26 | /* 1 = CLKIN / 2 */ |
| 27 | #define CONFIG_CLKIN_HALF 0 |
| 28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
| 29 | /* 1 = bypass PLL */ |
| 30 | #define CONFIG_PLL_BYPASS 0 |
| 31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
| 32 | /* Values can range from 0-63 (where 0 means 64) */ |
| 33 | #define CONFIG_VCO_MULT 20 |
| 34 | /* CCLK_DIV controls the core clock divider */ |
| 35 | /* Values can be 1, 2, 4, or 8 ONLY */ |
| 36 | #define CONFIG_CCLK_DIV 1 |
| 37 | /* SCLK_DIV controls the system clock divider */ |
| 38 | /* Values can range from 1-15 */ |
| 39 | #define CONFIG_SCLK_DIV 6 |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 40 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 41 | |
| 42 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 43 | * Memory Settings |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 44 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 45 | #define CONFIG_MEM_ADD_WDTH 9 |
| 46 | #define CONFIG_MEM_SIZE 64 |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 47 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 48 | #define CONFIG_EBIU_SDRRC_VAL 0x306 |
| 49 | #define CONFIG_EBIU_SDGCTL_VAL 0x91114d |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 50 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 51 | #define CONFIG_EBIU_AMGCTL_VAL 0x3F |
| 52 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 |
| 53 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 54 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 55 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
| 56 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 57 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 58 | |
| 59 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 60 | * Network Settings |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 61 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 62 | #define ADI_CMDS_NETWORK 1 |
Ben Warren | 0fd6aae | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 63 | #define CONFIG_NET_MULTI |
| 64 | #define CONFIG_SMC91111 1 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 65 | #define CONFIG_SMC91111_BASE 0x2C010300 |
| 66 | #define CONFIG_SMC_USE_32_BIT 1 |
| 67 | #define CONFIG_HOSTNAME bf561-ezkit |
| 68 | /* Uncomment next line to use fixed MAC address */ |
| 69 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 70 | |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 71 | |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 72 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 73 | * Flash Settings |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 74 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 75 | #define CONFIG_SYS_FLASH_CFI |
| 76 | #define CONFIG_FLASH_CFI_DRIVER |
| 77 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET |
| 78 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| 79 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 80 | #define CONFIG_SYS_MAX_FLASH_SECT 135 |
| 81 | /* The BF561-EZKIT uses a top boot flash */ |
| 82 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 83 | #define CONFIG_ENV_ADDR 0x20004000 |
| 84 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) |
| 85 | #define CONFIG_ENV_SIZE 0x2000 |
| 86 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 87 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
| 88 | #define ENV_IS_EMBEDDED |
| 89 | #else |
Mike Frysinger | 45b57bd | 2009-07-21 22:17:36 -0400 | [diff] [blame] | 90 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 91 | #endif |
Mike Frysinger | 37f4870 | 2009-06-14 06:29:07 -0400 | [diff] [blame] | 92 | #ifdef ENV_IS_EMBEDDED |
| 93 | /* WARNING - the following is hand-optimized to fit within |
| 94 | * the sector before the environment sector. If it throws |
| 95 | * an error during compilation remove an object here to get |
| 96 | * it linked after the configuration sector. |
| 97 | */ |
| 98 | # define LDS_BOARD_TEXT \ |
Peter Tyser | 12e5765 | 2010-04-12 22:28:13 -0500 | [diff] [blame] | 99 | arch/blackfin/cpu/traps.o (.text .text.*); \ |
| 100 | arch/blackfin/cpu/interrupt.o (.text .text.*); \ |
| 101 | arch/blackfin/cpu/serial.o (.text .text.*); \ |
Mike Frysinger | 37f4870 | 2009-06-14 06:29:07 -0400 | [diff] [blame] | 102 | common/dlmalloc.o (.text .text.*); \ |
Peter Tyser | 685b7f5 | 2010-04-12 22:28:05 -0500 | [diff] [blame] | 103 | lib/crc32.o (.text .text.*); \ |
| 104 | lib/zlib.o (.text .text.*); \ |
Mike Frysinger | 37f4870 | 2009-06-14 06:29:07 -0400 | [diff] [blame] | 105 | board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \ |
| 106 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 107 | common/env_embedded.o (.text .text.*); |
| 108 | #endif |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 109 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 110 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 111 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 112 | * I2C Settings |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 113 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 114 | #define CONFIG_SOFT_I2C |
| 115 | #ifdef CONFIG_SOFT_I2C |
| 116 | #define PF_SCL PF0 |
| 117 | #define PF_SDA PF1 |
| 118 | #define I2C_INIT \ |
| 119 | do { \ |
| 120 | *pFIO0_DIR |= PF_SCL; \ |
| 121 | SSYNC(); \ |
| 122 | } while (0) |
| 123 | #define I2C_ACTIVE \ |
| 124 | do { \ |
| 125 | *pFIO0_DIR |= PF_SDA; \ |
| 126 | *pFIO0_INEN &= ~PF_SDA; \ |
| 127 | SSYNC(); \ |
| 128 | } while (0) |
| 129 | #define I2C_TRISTATE \ |
| 130 | do { \ |
| 131 | *pFIO0_DIR &= ~PF_SDA; \ |
| 132 | *pFIO0_INEN |= PF_SDA; \ |
| 133 | SSYNC(); \ |
| 134 | } while (0) |
| 135 | #define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0) |
| 136 | #define I2C_SDA(bit) \ |
| 137 | do { \ |
| 138 | if (bit) \ |
| 139 | *pFIO0_FLAG_S = PF_SDA; \ |
| 140 | else \ |
| 141 | *pFIO0_FLAG_C = PF_SDA; \ |
| 142 | SSYNC(); \ |
| 143 | } while (0) |
| 144 | #define I2C_SCL(bit) \ |
| 145 | do { \ |
| 146 | if (bit) \ |
| 147 | *pFIO0_FLAG_S = PF_SCL; \ |
| 148 | else \ |
| 149 | *pFIO0_FLAG_C = PF_SCL; \ |
| 150 | SSYNC(); \ |
| 151 | } while (0) |
| 152 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 153 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 154 | #define CONFIG_SYS_I2C_SPEED 50000 |
| 155 | #define CONFIG_SYS_I2C_SLAVE 0 |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 156 | #endif |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 157 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 158 | |
| 159 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 160 | * Misc Settings |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 161 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 162 | #define CONFIG_UART_CONSOLE 0 |
| 163 | |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 164 | |
| 165 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 166 | * Pull in common ADI header for remaining command/environment setup |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 167 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 168 | #include <configs/bfin_adi_common.h> |
Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame] | 169 | |
Mike Frysinger | 18a407c | 2009-04-24 17:22:40 -0400 | [diff] [blame] | 170 | #endif |