| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Akshay Saraswat | fdd9df3 | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 Samsung Electronics |
| 4 | * |
| 5 | * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board. |
| Akshay Saraswat | fdd9df3 | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_PEACH_PIT_H |
| 9 | #define __CONFIG_PEACH_PIT_H |
| 10 | |
| Sjoerd Simons | b2d517b | 2015-03-12 22:33:29 +0100 | [diff] [blame] | 11 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 12 | "bootm_size=0x10000000\0" \ |
| 13 | "kernel_addr_r=0x22000000\0" \ |
| 14 | "fdt_addr_r=0x23000000\0" \ |
| 15 | "ramdisk_addr_r=0x23300000\0" \ |
| 16 | "scriptaddr=0x30000000\0" \ |
| 17 | "pxefile_addr_r=0x31000000\0" |
| 18 | |
| Simon Glass | 252747a | 2014-10-07 22:01:46 -0600 | [diff] [blame] | 19 | #include <configs/exynos5420-common.h> |
| Simon Glass | fbff18d | 2014-10-07 22:01:47 -0600 | [diff] [blame] | 20 | #include <configs/exynos5-dt-common.h> |
| Simon Glass | 0b18b80 | 2015-08-03 08:19:29 -0600 | [diff] [blame] | 21 | #include <configs/exynos5-common.h> |
| Akshay Saraswat | fdd9df3 | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 22 | |
| Hyungwon Hwang | aa6bd5d | 2014-12-12 14:45:44 +0900 | [diff] [blame] | 23 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| Hyungwon Hwang | aa6bd5d | 2014-12-12 14:45:44 +0900 | [diff] [blame] | 24 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) |
| 25 | |
| Akshay Saraswat | 926aa81 | 2014-11-13 22:38:19 +0530 | [diff] [blame] | 26 | /* DRAM Memory Banks */ |
| Akshay Saraswat | 926aa81 | 2014-11-13 22:38:19 +0530 | [diff] [blame] | 27 | #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ |
| 28 | |
| Akshay Saraswat | fdd9df3 | 2014-06-18 17:53:58 +0530 | [diff] [blame] | 29 | #endif /* __CONFIG_PEACH_PIT_H */ |