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git01.mediatek.com / filogic / uboot / 844493d7e99cb795f3e28130ee09ba7a6441162f / . / src / arm / nxp / imx / imx6qdl-mba6.dtsi
blob: 8cefda70db638479c2b4d57dc20e23a8a48f9093 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2013 Sascha Hauer, Pengutronix
4 *
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 */
8
9#include <dt-bindings/clock/imx6qdl-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/sound/fsl-imx-audmux.h>
13
14/ {
15 aliases {
16 mmc0 = &usdhc3;
17 mmc1 = &usdhc2;
18 /delete-property/ mmc2;
19 /delete-property/ mmc3;
20 rtc0 = &rtc0;
21 };
22
23 chosen {
24 stdout-path = &uart2;
25 };
26
27 beeper: gpio-beeper {
28 compatible = "gpio-beeper";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpiobeeper>;
31 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
32 };
33
34 gpio_buttons: gpio-buttons {
35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpiobuttons>;
38
39 button-1 {
40 label = "s6";
41 linux,code = <KEY_F6>;
42 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
43 wakeup-source;
44 };
45
46 button-2 {
47 label = "s7";
48 linux,code = <KEY_F7>;
49 gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
50 wakeup-source;
51 };
52
53 button-3 {
54 label = "s8";
55 linux,code = <KEY_F8>;
56 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
57 wakeup-source;
58 };
59 };
60
61 gpio-leds {
62 compatible = "gpio-leds";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_gpioled>;
65
66 led1 {
67 label = "led1";
68 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
69 linux,default-trigger = "default-on";
70 };
71
72 led2 {
73 label = "led2";
74 gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
75 linux,default-trigger = "heartbeat";
76 };
77 };
78
79 reg_mba6_3p3v: regulator-mba6-3p3v {
80 compatible = "regulator-fixed";
81 regulator-name = "supply-mba6-3p3v";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-always-on;
85 };
86
87 reg_pcie: regulator-pcie {
88 compatible = "regulator-fixed";
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_regpcie>;
91 regulator-name = "supply-pcie";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 /* PCIE.PWR_EN */
95 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
96 enable-active-high;
97 regulator-always-on;
98 vin-supply = <&reg_mba6_3p3v>;
99 };
100
101 reg_vcc3v3_audio: regulator-vcc3v3-audio {
102 compatible = "regulator-fixed";
103 regulator-name = "vcc3v3-audio";
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 vin-supply = <&reg_mba6_3p3v>;
107 };
108
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame^]109 reserved-memory {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges;
113
114 linux,cma {
115 compatible = "shared-dma-pool";
116 reusable;
117 size = <0x14000000>;
118 alloc-ranges = <0x10000000 0x20000000>;
119 linux,cma-default;
120 };
121 };
122
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]123 sound {
124 compatible = "fsl,imx-audio-tlv320aic32x4";
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_audmux>;
127 model = "imx-audio-tlv320aic32x4";
128 ssi-controller = <&ssi1>;
129 audio-codec = <&tlv320aic32x4>;
130 audio-asrc = <&asrc>;
131 audio-routing =
132 "IN3_L", "Mic Jack",
133 "Mic Jack", "Mic Bias",
134 "IN1_L", "Line In Jack",
135 "IN1_R", "Line In Jack",
136 "Line Out Jack", "LOL",
137 "Line Out Jack", "LOR";
138 mux-int-port = <1>;
139 mux-ext-port = <3>;
140 };
141};
142
143&audmux {
144 status = "okay";
145
146 mux-ssi0 {
147 fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>;
148 fsl,port-config = <
149 (IMX_AUDMUX_V2_PTCR_SYN |
150 IMX_AUDMUX_V2_PTCR_TFSDIR |
151 IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) |
152 IMX_AUDMUX_V2_PTCR_TCLKDIR |
153 IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3))
154 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)
155 >;
156 };
157
158 mux-aud3 {
159 fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>;
160 fsl,port-config = <
161 IMX_AUDMUX_V2_PTCR_SYN
162 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0)
163 >;
164 };
165};
166
167&can1 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_can1>;
170 status = "okay";
171};
172
173&can2 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_can2>;
176 status = "okay";
177};
178
179&ecspi1 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>;
182 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>;
183};
184
185&fec {
186 phy-mode = "rgmii-id";
187 phy-handle = <&ethphy>;
188 mac-address = [00 00 00 00 00 00];
189 status = "okay";
190
191 mdio {
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 ethphy: ethernet-phy@3 {
196 compatible = "ethernet-phy-ieee802.3-c22";
197 reg = <3>;
198 interrupt-parent = <&gpio1>;
199 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
200 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
201 reset-assert-us = <1000>;
202 reset-deassert-us = <100000>;
203 micrel,force-master;
204 max-speed = <1000>;
205 };
206 };
207};
208
209&hdmi {
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_hdmi>;
212 ddc-i2c-bus = <&i2c2>;
213 status = "okay";
214};
215
216&i2c1 {
217 tlv320aic32x4: audio-codec@18 {
218 compatible = "ti,tlv320aic32x4";
219 reg = <0x18>;
220 clocks = <&clks IMX6QDL_CLK_CKO>;
221 clock-names = "mclk";
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_codec>;
224 ldoin-supply = <&reg_vcc3v3_audio>;
225 iov-supply = <&reg_mba6_3p3v>;
226 };
227};
228
229/* DDC */
230&i2c2 {
231 clock-frequency = <100000>;
232 pinctrl-names = "default", "gpio";
233 pinctrl-0 = <&pinctrl_i2c2>;
234 pinctrl-1 = <&pinctrl_i2c2_recovery>;
235 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
236 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
237 status = "okay";
238};
239
240&pcie {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pcie>;
243 reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>;
244 vpcie-supply = <&reg_pcie>;
245 status = "okay";
246};
247
248&pwm1 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_pwm1>;
251 status = "okay";
252};
253
254&pwm3 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_pwm3>;
257 status = "okay";
258};
259
260&pwm4 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_pwm4>;
263 status = "okay";
264};
265
266&snvs_poweroff {
267 status = "okay";
268};
269
270&ssi1 {
271 status = "okay";
272};
273
274&uart2 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_uart2>;
277 status = "okay";
278};
279
280&uart3 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_uart3>;
283 uart-has-rtscts;
284 status = "okay";
285};
286
287&uart4 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_uart4>;
290 uart-has-rtscts;
291 linux,rs485-enabled-at-boot-time;
292 rs485-rts-active-low;
293 rs485-rx-during-tx;
294 status = "okay";
295};
296
297&uart5 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart5>;
300 uart-has-rtscts;
301 status = "okay";
302};
303
304&usbh1 {
305 disable-over-current;
306 status = "okay";
307 #address-cells = <1>;
308 #size-cells = <0>;
309
310 hub@1 {
311 compatible = "usb424,2517";
312 reg = <1>;
313 #address-cells = <1>;
314 #size-cells = <0>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]315 vdd-supply = <&reg_mba6_3p3v>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]316
317 ethernet@1 {
318 compatible = "usb424,9e00";
319 reg = <1>;
320 nvmem-cells = <&mba_mac_address>;
321 nvmem-cell-names = "mac-address";
322 };
323 };
324};
325
326&usbotg {
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_usbotg>;
329 power-active-high;
330 over-current-active-low;
331 srp-disable;
332 hnp-disable;
333 adp-disable;
334 dr_mode = "otg";
335 status = "okay";
336};
337
338/* SD card slot */
339&usdhc2 {
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_usdhc2>;
342 vmmc-supply = <&reg_mba6_3p3v>;
343 bus-width = <4>;
344 no-1-8-v;
345 no-mmc;
346 no-sdio;
347 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
348 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
349 status = "okay";
350};
351
352&wdog1 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_wdog1>;
355 /* does not work on unmodified starter kit */
356 /* fsl,ext-reset-output; */
357 status = "okay";
358};
359
360&iomuxc {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_hog>;
363
364 pinctrl_audmux: audmuxgrp {
365 fsl,pins = <
366 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
367 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
368 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
369 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
370 >;
371 };
372
373 pinctrl_can1: can1grp {
374 fsl,pins = <
375 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099
376 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099
377 >;
378 };
379
380 pinctrl_can2: can2grp {
381 fsl,pins = <
382 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099
383 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099
384 >;
385 };
386
387 pinctrl_codec: codecgrp {
388 fsl,pins = <
389 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */
390 >;
391 };
392
393 pinctrl_ecspi1_mba6: ecspimba6grp {
394 fsl,pins = <
395 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */
396 >;
397 };
398
399 pinctrl_enet: enetgrp {
400 fsl,pins = <
401 /* FEC phy IRQ */
402 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
403 /* FEC phy reset */
404 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
405 /* DSE = 100, 100k up, SPEED = MED */
406 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
407 MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
408 /* DSE = 111, pull 100k up */
409 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
410 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
411 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
412 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
413 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
414 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
415 /* DSE = 111, pull external */
416 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
417 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
418 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
419 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
420 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
421 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
422 /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
423 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
424 >;
425 };
426
427 pinctrl_gpiobeeper: gpiobeepergrp {
428 fsl,pins = <
429 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099
430 >;
431 };
432
433 pinctrl_gpiobuttons: gpiobuttongrp {
434 fsl,pins = <
435 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099
436 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099
437 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099
438 >;
439 };
440
441 pinctrl_gpioled: gpioledgrp {
442 fsl,pins = <
443 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */
444 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */
445 >;
446 };
447
448 pinctrl_hdmi: hdmigrp {
449 /* NOTE: DDC is done via I2C2, so DON'T
450 * configure DDC pins for HDMI!
451 */
452 fsl,pins = <
453 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
454 >;
455 };
456
457 pinctrl_hog: hoggrp {
458 fsl,pins = <
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]459 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
460 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
461 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
462
463 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
464 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
465 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
466 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
467 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
468 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
469 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
470
471 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
472 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
473 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
474 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
475 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
476
477 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
478 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
479 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
480 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
481
482 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
483 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
484 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
485
486 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
487 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
488 >;
489 };
490
491 pinctrl_i2c2: i2c2grp {
492 fsl,pins = <
493 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
494 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
495 >;
496 };
497
498 pinctrl_i2c2_recovery: i2c2recoverygrp {
499 fsl,pins = <
500 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899
501 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899
502 >;
503 };
504
505 pinctrl_pcie: pciegrp {
506 fsl,pins = <
507 /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/
508 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */
509 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */
510 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */
511 >;
512 };
513
514 pinctrl_pwm1: pwm1grp {
515 fsl,pins = <
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]516 /* 100 k PD, DSE 120 OHM, SPEED LO */
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]517 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
518 >;
519 };
520
521 pinctrl_pwm3: pwm3grp {
522 fsl,pins = <
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]523 /* 100 k PD, DSE 120 OHM, SPEED LO */
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]524 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
525 >;
526 };
527
528 pinctrl_pwm4: pwm4grp {
529 fsl,pins = <
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]530 /* 100 k PD, DSE 120 OHM, SPEED LO */
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]531 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
532 >;
533 };
534
535 pinctrl_regpcie: regpciegrp {
536 fsl,pins = <
537 /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/
538 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */
539 >;
540 };
541
542 pinctrl_uart2: uart2grp {
543 fsl,pins = <
544 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
545 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
546 >;
547 };
548
549 pinctrl_uart3: uart3grp {
550 fsl,pins = <
551 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
552 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
553 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
554 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
555 >;
556 };
557
558 pinctrl_uart4: uart4grp {
559 fsl,pins = <
560 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
561 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
562 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
563 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
564 >;
565 };
566
567 pinctrl_uart5: uart5grp {
568 fsl,pins = <
569 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
570 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
571 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
572 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1
573 >;
574 };
575
576 pinctrl_usdhc2: usdhc2grp {
577 fsl,pins = <
578 /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
579 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
580 /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
581 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
582 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
583 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
584 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
585 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
586
587 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
588 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
589 >;
590 };
591
592 pinctrl_usbotg: usbotggrp {
593 fsl,pins = <
594 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
595 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
596 MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099
597 >;
598 };
599
600 pinctrl_wdog1: wdog1grp {
601 fsl,pins = <
602 /* Watchdog out */
603 MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099
604 >;
605 };
606};