| Tom Rini | 844493d | 2025-01-26 16:17:47 -0600 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| 2 | |
| 3 | #ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H |
| 4 | #define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H |
| 5 | |
| 6 | #define CLK_TOP_AD_SYS_26M_CK 0 |
| 7 | #define CLK_TOP_CLKPH_MCK_O 1 |
| 8 | #define CLK_TOP_DMPLL 2 |
| 9 | #define CLK_TOP_DPI_CK 3 |
| 10 | #define CLK_TOP_WHPLL_AUDIO_CK 4 |
| 11 | |
| 12 | #define CLK_TOP_SYSPLL_D2 5 |
| 13 | #define CLK_TOP_SYSPLL_D3 6 |
| 14 | #define CLK_TOP_SYSPLL_D5 7 |
| 15 | #define CLK_TOP_SYSPLL1_D2 8 |
| 16 | #define CLK_TOP_SYSPLL1_D4 9 |
| 17 | #define CLK_TOP_SYSPLL1_D8 10 |
| 18 | #define CLK_TOP_SYSPLL1_D16 11 |
| 19 | #define CLK_TOP_SYSPLL2_D2 12 |
| 20 | #define CLK_TOP_SYSPLL2_D4 13 |
| 21 | #define CLK_TOP_SYSPLL3_D2 14 |
| 22 | #define CLK_TOP_SYSPLL3_D4 15 |
| 23 | #define CLK_TOP_SYSPLL4_D2 16 |
| 24 | #define CLK_TOP_SYSPLL4_D4 17 |
| 25 | #define CLK_TOP_UNIVPLL_D2 18 |
| 26 | #define CLK_TOP_UNIVPLL_D3 19 |
| 27 | #define CLK_TOP_UNIVPLL_D5 20 |
| 28 | #define CLK_TOP_UNIVPLL_D26 21 |
| 29 | #define CLK_TOP_UNIVPLL1_D2 22 |
| 30 | #define CLK_TOP_UNIVPLL1_D4 23 |
| 31 | #define CLK_TOP_UNIVPLL1_D8 24 |
| 32 | #define CLK_TOP_UNIVPLL2_D2 25 |
| 33 | #define CLK_TOP_UNIVPLL2_D4 26 |
| 34 | #define CLK_TOP_UNIVPLL2_D8 27 |
| 35 | #define CLK_TOP_UNIVPLL3_D2 28 |
| 36 | #define CLK_TOP_UNIVPLL3_D4 29 |
| 37 | #define CLK_TOP_MSDCPLL_D2 30 |
| 38 | #define CLK_TOP_MSDCPLL_D4 31 |
| 39 | #define CLK_TOP_MSDCPLL_D8 32 |
| 40 | #define CLK_TOP_MSDCPLL_D16 33 |
| 41 | #define CLK_TOP_VENCPLL_D3 34 |
| 42 | #define CLK_TOP_TVDPLL_D2 35 |
| 43 | #define CLK_TOP_TVDPLL_D4 36 |
| 44 | #define CLK_TOP_DMPLL_D2 37 |
| 45 | #define CLK_TOP_DMPLL_D4 38 |
| 46 | #define CLK_TOP_DMPLL_D8 39 |
| 47 | #define CLK_TOP_AD_SYS_26M_D2 40 |
| 48 | |
| 49 | #define CLK_TOP_AXI_SEL 41 |
| 50 | #define CLK_TOP_MEM_SEL 42 |
| 51 | #define CLK_TOP_DDRPHY_SEL 43 |
| 52 | #define CLK_TOP_MM_SEL 44 |
| 53 | #define CLK_TOP_PWM_SEL 45 |
| 54 | #define CLK_TOP_VDEC_SEL 46 |
| 55 | #define CLK_TOP_MFG_SEL 47 |
| 56 | #define CLK_TOP_CAMTG_SEL 48 |
| 57 | #define CLK_TOP_UART_SEL 49 |
| 58 | #define CLK_TOP_SPI_SEL 50 |
| 59 | #define CLK_TOP_USB20_SEL 51 |
| 60 | #define CLK_TOP_MSDC50_0_SEL 52 |
| 61 | #define CLK_TOP_MSDC30_0_SEL 53 |
| 62 | #define CLK_TOP_MSDC30_1_SEL 54 |
| 63 | #define CLK_TOP_MSDC30_2_SEL 55 |
| 64 | #define CLK_TOP_MSDC30_3_SEL 56 |
| 65 | #define CLK_TOP_AUDIO_SEL 57 |
| 66 | #define CLK_TOP_AUDINTBUS_SEL 58 |
| 67 | #define CLK_TOP_PMICSPI_SEL 59 |
| 68 | #define CLK_TOP_SCP_SEL 60 |
| 69 | #define CLK_TOP_ATB_SEL 61 |
| 70 | #define CLK_TOP_DPI0_SEL 62 |
| 71 | #define CLK_TOP_SCAM_SEL 63 |
| 72 | #define CLK_TOP_MFG13M_SEL 64 |
| 73 | #define CLK_TOP_AUD1_SEL 65 |
| 74 | #define CLK_TOP_AUD2_SEL 66 |
| 75 | #define CLK_TOP_IRDA_SEL 67 |
| 76 | #define CLK_TOP_IRTX_SEL 68 |
| 77 | #define CLK_TOP_DISPPWM_SEL 69 |
| 78 | |
| 79 | #endif |