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git01.mediatek.com / filogic / uboot / 8444550fa9014ad3e71baa61c6ffa6f4ab6f5e18 / . / board / purism / librem5 / lpddr4_timing.c
blob: 46bc7f8591cbf850d6ad85d5c4e5cf42b15c278d [file] [log] [blame]
Angus Ainslie3f8667c2022-08-25 06:46:02 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <linux/kernel.h>
7#include <common.h>
8#include <asm/arch/ddr.h>
9#include <asm/arch/lpddr4_define.h>
10
11#define WR_POST_EXT_3200 /* recommened to define */
12
13struct dram_cfg_param lpddr4_ddrc_cfg[] = {
14 /* Start to config, default 3200mbps */
15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
23#ifdef WR_POST_EXT_3200
24 { DDRC_INIT4(0), 0x00330008 },
25#else
26 { DDRC_INIT4(0), 0x00310008 },
27#endif
28 { DDRC_INIT6(0), 0x0066004a },
29 { DDRC_INIT7(0), 0x0006004a },
30
31 { DDRC_DRAMTMG0(0), 0x1A201B22 },
32 { DDRC_DRAMTMG1(0), 0x00060633 },
33 { DDRC_DRAMTMG3(0), 0x00C0C000 },
34 { DDRC_DRAMTMG4(0), 0x0F04080F },
35 { DDRC_DRAMTMG5(0), 0x02040C0C },
36 { DDRC_DRAMTMG6(0), 0x01010007 },
37 { DDRC_DRAMTMG7(0), 0x00000401 },
38 { DDRC_DRAMTMG12(0), 0x00020600 },
39 { DDRC_DRAMTMG13(0), 0x0C100002 },
40 { DDRC_DRAMTMG14(0), 0x000000E6 },
41 { DDRC_DRAMTMG17(0), 0x00A00050 },
42
43 { DDRC_ZQCTL0(0), 0x03200018 },
44 { DDRC_ZQCTL1(0), 0x028061A8 },
45 { DDRC_ZQCTL2(0), 0x00000000 },
46
47 { DDRC_DFITMG0(0), 0x0497820A },
48 { DDRC_DFITMG1(0), 0x00080303 },
49 { DDRC_DFIUPD0(0), 0xE0400018 },
50 { DDRC_DFIUPD1(0), 0x00DF00E4 },
51 { DDRC_DFIUPD2(0), 0x80000000 },
52 { DDRC_DFIMISC(0), 0x00000011 },
53 { DDRC_DFITMG2(0), 0x0000170A },
54
55 { DDRC_DBICTL(0), 0x00000001 },
56 { DDRC_DFIPHYMSTR(0), 0x00000001 },
57 { DDRC_RANKCTL(0), 0x00000c99 },
58 { DDRC_DRAMTMG2(0), 0x070E171a },
59
60 /* address mapping */
61 { DDRC_ADDRMAP0(0), 0x00000015 },
62 { DDRC_ADDRMAP3(0), 0x00000000 },
63 { DDRC_ADDRMAP4(0), 0x00001F1F },
64 /* bank interleave */
65 { DDRC_ADDRMAP1(0), 0x00080808 },
66 { DDRC_ADDRMAP5(0), 0x07070707 },
67 { DDRC_ADDRMAP6(0), 0x08080707 },
68
69 /* performance setting */
70 { DDRC_ODTCFG(0), 0x0b060908 },
71 { DDRC_ODTMAP(0), 0x00000000 },
72 { DDRC_SCHED(0), 0x29511505 },
73 { DDRC_SCHED1(0), 0x0000002c },
74 { DDRC_PERFHPR1(0), 0x5900575b },
75 /* 150T starve and 0x90 max tran len */
76 { DDRC_PERFLPR1(0), 0x90000096 },
77 /* 300T starve and 0x10 max tran len */
78 { DDRC_PERFWR1(0), 0x1000012c },
79 { DDRC_DBG0(0), 0x00000016 },
80 { DDRC_DBG1(0), 0x00000000 },
81 { DDRC_DBGCMD(0), 0x00000000 },
82 { DDRC_SWCTL(0), 0x00000001 },
83 { DDRC_POISONCFG(0), 0x00000011 },
84 { DDRC_PCCFG(0), 0x00000111 },
85 { DDRC_PCFGR_0(0), 0x000010f3 },
86 { DDRC_PCFGW_0(0), 0x000072ff },
87 { DDRC_PCTRL_0(0), 0x00000001 },
88 /* disable Read Qos*/
89 { DDRC_PCFGQOS0_0(0), 0x00000e00 },
90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
91 /* disable Write Qos*/
92 { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
93 { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
94
95 /* Frequency 1: 400mbps */
96 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
97 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
98 { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
99 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
100 { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
101 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
102 { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
103 { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
104 { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
105 { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
106 { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
107 { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
108 { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
109 { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
110 { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
111 { DDRC_FREQ1_INIT3(0), 0x00840000 },
112 { DDRC_FREQ1_INIT4(0), 0x00310008 },
113 { DDRC_FREQ1_INIT6(0), 0x0066004a },
114 { DDRC_FREQ1_INIT7(0), 0x0006004a },
115
116 /* Frequency 2: 100mbps */
117 { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
118 { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
119 { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
120 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
121 { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
122 { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
123 { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
124 { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
125 { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
126 { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
127 { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
128 { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
129 { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
130 { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
131 { DDRC_FREQ2_INIT3(0), 0x00840000 },
132 { DDRC_FREQ2_INIT4(0), 0x00310008 },
133 { DDRC_FREQ2_INIT6(0), 0x0066004a },
134 { DDRC_FREQ2_INIT7(0), 0x0006004a },
135};
136
137/* PHY Initialize Configuration */
138struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
139 { 0x20110, 0x02 },
140 { 0x20111, 0x03 },
141 { 0x20112, 0x04 },
142 { 0x20113, 0x05 },
143 { 0x20114, 0x00 },
144 { 0x20115, 0x01 },
145
146 { 0x1005f, 0x1ff },
147 { 0x1015f, 0x1ff },
148 { 0x1105f, 0x1ff },
149 { 0x1115f, 0x1ff },
150 { 0x1205f, 0x1ff },
151 { 0x1215f, 0x1ff },
152 { 0x1305f, 0x1ff },
153 { 0x1315f, 0x1ff },
154
155 { 0x11005f, 0x1ff },
156 { 0x11015f, 0x1ff },
157 { 0x11105f, 0x1ff },
158 { 0x11115f, 0x1ff },
159 { 0x11205f, 0x1ff },
160 { 0x11215f, 0x1ff },
161 { 0x11305f, 0x1ff },
162 { 0x11315f, 0x1ff },
163
164 { 0x21005f, 0x1ff },
165 { 0x21015f, 0x1ff },
166 { 0x21105f, 0x1ff },
167 { 0x21115f, 0x1ff },
168 { 0x21205f, 0x1ff },
169 { 0x21215f, 0x1ff },
170 { 0x21305f, 0x1ff },
171 { 0x21315f, 0x1ff },
172
173 { 0x55, 0x1ff },
174 { 0x1055, 0x1ff },
175 { 0x2055, 0x1ff },
176 { 0x3055, 0x1ff },
177 { 0x4055, 0x1ff },
178 { 0x5055, 0x1ff },
179 { 0x6055, 0x1ff },
180 { 0x7055, 0x1ff },
181 { 0x8055, 0x1ff },
182 { 0x9055, 0x1ff },
183
184 { 0x200c5, 0x19 },
185 { 0x1200c5, 0x7 },
186 { 0x2200c5, 0x7 },
187
188 { 0x2002e, 0x2 },
189 { 0x12002e, 0x2 },
190 { 0x22002e, 0x2 },
191
192 { 0x90204, 0x0 },
193 { 0x190204, 0x0 },
194 { 0x290204, 0x0 },
195
196#ifdef WR_POST_EXT_3200
197 { 0x20024, 0xeb },
198#else
199 { 0x20024, 0xab },
200#endif
201 { 0x2003a, 0x0 },
202 { 0x120024, 0xab },
203 { 0x2003a, 0x0 },
204 { 0x220024, 0xab },
205 { 0x2003a, 0x0 },
206 { 0x20056, 0x3 },
207 { 0x120056, 0xa },
208 { 0x220056, 0xa },
209 { 0x1004d, 0xe00 },
210 { 0x1014d, 0xe00 },
211 { 0x1104d, 0xe00 },
212 { 0x1114d, 0xe00 },
213 { 0x1204d, 0xe00 },
214 { 0x1214d, 0xe00 },
215 { 0x1304d, 0xe00 },
216 { 0x1314d, 0xe00 },
217 { 0x11004d, 0xe00 },
218 { 0x11014d, 0xe00 },
219 { 0x11104d, 0xe00 },
220 { 0x11114d, 0xe00 },
221 { 0x11204d, 0xe00 },
222 { 0x11214d, 0xe00 },
223 { 0x11304d, 0xe00 },
224 { 0x11314d, 0xe00 },
225 { 0x21004d, 0xe00 },
226 { 0x21014d, 0xe00 },
227 { 0x21104d, 0xe00 },
228 { 0x21114d, 0xe00 },
229 { 0x21204d, 0xe00 },
230 { 0x21214d, 0xe00 },
231 { 0x21304d, 0xe00 },
232 { 0x21314d, 0xe00 },
233
234 { 0x10049, 0xfbe },
235 { 0x10149, 0xfbe },
236 { 0x11049, 0xfbe },
237 { 0x11149, 0xfbe },
238 { 0x12049, 0xfbe },
239 { 0x12149, 0xfbe },
240 { 0x13049, 0xfbe },
241 { 0x13149, 0xfbe },
242 { 0x110049, 0xfbe },
243 { 0x110149, 0xfbe },
244 { 0x111049, 0xfbe },
245 { 0x111149, 0xfbe },
246 { 0x112049, 0xfbe },
247 { 0x112149, 0xfbe },
248 { 0x113049, 0xfbe },
249 { 0x113149, 0xfbe },
250 { 0x210049, 0xfbe },
251 { 0x210149, 0xfbe },
252 { 0x211049, 0xfbe },
253 { 0x211149, 0xfbe },
254 { 0x212049, 0xfbe },
255 { 0x212149, 0xfbe },
256 { 0x213049, 0xfbe },
257 { 0x213149, 0xfbe },
258
259 { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
260 { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
261 { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
262 { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
263 { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
264 { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
265 { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
266 { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
267 { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
268 { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
269
270 { 0x20018, 0x3 },
271 { 0x20075, 0x4 },
272 { 0x20050, 0x0 },
273 { 0x20008, 0x320 },
274 { 0x120008, 0x64 },
275 { 0x220008, 0x19 },
276 { 0x20088, 0x9 },
277 { 0x200b2, 0x104 },
278 { 0x10043, 0x5a1 },
279 { 0x10143, 0x5a1 },
280 { 0x11043, 0x5a1 },
281 { 0x11143, 0x5a1 },
282 { 0x12043, 0x5a1 },
283 { 0x12143, 0x5a1 },
284 { 0x13043, 0x5a1 },
285 { 0x13143, 0x5a1 },
286 { 0x1200b2, 0x104 },
287 { 0x110043, 0x5a1 },
288 { 0x110143, 0x5a1 },
289 { 0x111043, 0x5a1 },
290 { 0x111143, 0x5a1 },
291 { 0x112043, 0x5a1 },
292 { 0x112143, 0x5a1 },
293 { 0x113043, 0x5a1 },
294 { 0x113143, 0x5a1 },
295 { 0x2200b2, 0x104 },
296 { 0x210043, 0x5a1 },
297 { 0x210143, 0x5a1 },
298 { 0x211043, 0x5a1 },
299 { 0x211143, 0x5a1 },
300 { 0x212043, 0x5a1 },
301 { 0x212143, 0x5a1 },
302 { 0x213043, 0x5a1 },
303 { 0x213143, 0x5a1 },
304 { 0x200fa, 0x1 },
305 { 0x1200fa, 0x1 },
306 { 0x2200fa, 0x1 },
307 { 0x20019, 0x1 },
308 { 0x120019, 0x1 },
309 { 0x220019, 0x1 },
310 { 0x200f0, 0x660 },
311 { 0x200f1, 0x0 },
312 { 0x200f2, 0x4444 },
313 { 0x200f3, 0x8888 },
314 { 0x200f4, 0x5665 },
315 { 0x200f5, 0x0 },
316 { 0x200f6, 0x0 },
317 { 0x200f7, 0xf000 },
318 { 0x20025, 0x0 },
319 { 0x2002d, 0x0 },
320 { 0x12002d, 0x0 },
321 { 0x22002d, 0x0 },
322
323 { 0x200c7, 0x80 },
324 { 0x1200c7, 0x80 },
325 { 0x2200c7, 0x80 },
326 { 0x200ca, 0x106 },
327 { 0x1200ca, 0x106 },
328 { 0x2200ca, 0x106 },
329};
330
331/* P0 message block paremeter for training firmware */
332struct dram_cfg_param lpddr4_fsp0_cfg[] = {
333 { 0xd0000, 0x0 },
334 { 0x54000, 0x0 },
335 { 0x54001, 0x0 },
336 { 0x54002, 0x0 },
337 { 0x54003, 0xc80 },
338 { 0x54004, 0x2 },
339 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
340 { 0x54006, LPDDR4_PHY_VREF_VALUE },
341 { 0x54007, 0x0 },
342 { 0x54008, 0x131f },
343 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
344 { 0x5400a, 0x0 },
345 { 0x5400b, 0x2 },
346 { 0x5400c, 0x0 },
347 { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
348 { 0x5400e, 0x0 },
349 { 0x5400f, 0x0 },
350 { 0x54010, 0x0 },
351 { 0x54011, 0x0 },
352 { 0x54012, 0x310 },
353 { 0x54013, 0x0 },
354 { 0x54014, 0x0 },
355 { 0x54015, 0x0 },
356 { 0x54016, 0x0 },
357 { 0x54017, 0x0 },
358 { 0x54018, 0x0 },
359
360 { 0x54019, 0x2dd4 },
361#ifdef WR_POST_EXT_3200
362 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
363#else
364 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
365#endif
366 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
367 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
368 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
369 { 0x5401d, 0x0 },
370 { 0x5401e, LPDDR4_MR22_RANK0 },
371 { 0x5401f, 0x2dd4 },
372#ifdef WR_POST_EXT_3200
373 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
374#else
375 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
376#endif
377 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
378 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
379 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
380 { 0x54023, 0x0 },
381 { 0x54024, LPDDR4_MR22_RANK1 },
382
383 { 0x54025, 0x0 },
384 { 0x54026, 0x0 },
385 { 0x54027, 0x0 },
386 { 0x54028, 0x0 },
387 { 0x54029, 0x0 },
388 { 0x5402a, 0x0 },
389 { 0x5402b, 0x1000 },
390 { 0x5402c, 0x3 },
391 { 0x5402d, 0x0 },
392 { 0x5402e, 0x0 },
393 { 0x5402f, 0x0 },
394 { 0x54030, 0x0 },
395 { 0x54031, 0x0 },
396 { 0x54032, 0xd400 },
397 /* MR3/MR2 */
398#ifdef WR_POST_EXT_3200
399 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
400#else
401 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
402#endif
403 /* MR11/MR4 */
404 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
405 /* self:0x284d//MR13/MR12 */
406 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
407 /* MR16/MR14*/
408 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
409 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
410 /* MR1 */
411 { 0x54038, 0xd400 },
412 /* MR3/MR2 */
413#ifdef WR_POST_EXT_3200
414 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
415#else
416 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
417#endif
418 /* MR11/MR4 */
419 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
420 /* self:0x284d//MR13/MR12 */
421 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
422 /* MR16/MR14 */
423 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
424 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
425 /* { 0x5403d, 0x500 } */
426 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
427 { 0x5403e, 0x0 },
428 { 0x5403f, 0x0 },
429 { 0x54040, 0x0 },
430 { 0x54041, 0x0 },
431 { 0x54042, 0x0 },
432 { 0x54043, 0x0 },
433 { 0x54044, 0x0 },
434 { 0xd0000, 0x1 },
435};
436
437/* P1 message block paremeter for training firmware */
438struct dram_cfg_param lpddr4_fsp1_cfg[] = {
439 { 0xd0000, 0x0 },
440 { 0x54000, 0x0 },
441 { 0x54001, 0x0 },
442 { 0x54002, 0x101 },
443 { 0x54003, 0x190 },
444 { 0x54004, 0x2 },
445 /* PHY Ron/Rtt */
446 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
447 { 0x54006, LPDDR4_PHY_VREF_VALUE },
448 { 0x54007, 0x0 },
449 { 0x54008, LPDDR4_TRAIN_SEQ_400 },
450 { 0x54009, LPDDR4_HDT_CTL_400_1D },
451 { 0x5400a, 0x0 },
452 { 0x5400b, 0x2 },
453 { 0x5400c, 0x0 },
454 { 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
455 { 0x5400e, 0x0 },
456 { 0x5400f, 0x0 },
457 { 0x54010, 0x0 },
458 { 0x54011, 0x0 },
459 { 0x54012, 0x310 },
460 { 0x54013, 0x0 },
461 { 0x54014, 0x0 },
462 { 0x54015, 0x0 },
463 { 0x54016, 0x0 },
464 { 0x54017, 0x0 },
465 { 0x54018, 0x0 },
466 { 0x54019, 0x84 },
467 /* MR4/MR3 */
468 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
469 /* MR12/MR11 */
470 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
471 LPDDR4_RTT_DQ)/*0x4d46*/ },
472 /* self:0x4d28//MR14/MR13 */
473 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
474 { 0x5401d, 0x0 },
475 { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
476 { 0x5401f, 0x84 },
477 { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
478 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
479 LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
480 /* self:0x4d28//MR14/MR13 */
481 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
482 { 0x54023, 0x0 },
483 { 0x54024, LPDDR4_MR22_RANK1 },
484 { 0x54025, 0x0 },
485 { 0x54026, 0x0 },
486 { 0x54027, 0x0 },
487 { 0x54028, 0x0 },
488 { 0x54029, 0x0 },
489 { 0x5402a, 0x0 },
490 { 0x5402b, 0x1000 },
491 { 0x5402c, 0x3 },
492 { 0x5402d, 0x0 },
493 { 0x5402e, 0x0 },
494 { 0x5402f, 0x0 },
495 { 0x54030, 0x0 },
496 { 0x54031, 0x0 },
497 { 0x54032, 0x8400 },
498 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
499 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
500 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
501 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
502 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
503 { 0x54038, 0x8400 },
504 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
505 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
506 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
507 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
508 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
509 { 0x5403e, 0x0 },
510 { 0x5403f, 0x0 },
511 { 0x54040, 0x0 },
512 { 0x54041, 0x0 },
513 { 0x54042, 0x0 },
514 { 0x54043, 0x0 },
515 { 0x54044, 0x0 },
516 { 0xd0000, 0x1 },
517};
518
519/* P2 message block paremeter for training firmware */
520struct dram_cfg_param lpddr4_fsp2_cfg[] = {
521 { 0xd0000, 0x0 },
522 { 0x54000, 0x0 },
523 { 0x54001, 0x0 },
524 { 0x54002, 0x102 },
525 { 0x54003, 0x64 },
526 { 0x54004, 0x2 },
527 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
528 { 0x54006, LPDDR4_PHY_VREF_VALUE },
529 { 0x54007, 0x0 },
530 { 0x54008, LPDDR4_TRAIN_SEQ_100 },
531 { 0x54009, LPDDR4_HDT_CTL_100_1D },
532 { 0x5400a, 0x0 },
533 { 0x5400b, 0x2 },
534 { 0x5400c, 0x0 },
535 { 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
536 { 0x5400e, 0x0 },
537 { 0x5400f, 0x0 },
538 { 0x54010, 0x0 },
539 { 0x54011, 0x0 },
540 { 0x54012, 0x310 },
541 { 0x54013, 0x0 },
542 { 0x54014, 0x0 },
543 { 0x54015, 0x0 },
544 { 0x54016, 0x0 },
545 { 0x54017, 0x0 },
546 { 0x54018, 0x0 },
547 { 0x54019, 0x84 },
548 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
549 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
550 LPDDR4_RTT_DQ) },
551 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
552 { 0x5401d, 0x0 },
553 { 0x5401e, LPDDR4_MR22_RANK0 },
554 { 0x5401f, 0x84 },
555 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
556 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
557 LPDDR4_RTT_DQ) },
558 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
559 { 0x54023, 0x0 },
560 { 0x54024, LPDDR4_MR22_RANK1 },
561 { 0x54025, 0x0 },
562 { 0x54026, 0x0 },
563 { 0x54027, 0x0 },
564 { 0x54028, 0x0 },
565 { 0x54029, 0x0 },
566 { 0x5402a, 0x0 },
567 { 0x5402b, 0x1000 },
568 { 0x5402c, 0x3 },
569 { 0x5402d, 0x0 },
570 { 0x5402e, 0x0 },
571 { 0x5402f, 0x0 },
572 { 0x54030, 0x0 },
573 { 0x54031, 0x0 },
574 { 0x54032, 0x8400 },
575 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
576 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
577 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
578 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
579 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
580 { 0x54038, 0x8400 },
581 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
582 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
583 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
584 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
585 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
586 { 0x5403e, 0x0 },
587 { 0x5403f, 0x0 },
588 { 0x54040, 0x0 },
589 { 0x54041, 0x0 },
590 { 0x54042, 0x0 },
591 { 0x54043, 0x0 },
592 { 0x54044, 0x0 },
593 { 0xd0000, 0x1 },
594};
595
596/* P0 2D message block paremeter for training firmware */
597struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
598 { 0xd0000, 0x0 },
599 { 0x54000, 0x0 },
600 { 0x54001, 0x0 },
601 { 0x54002, 0x0 },
602 { 0x54003, 0xc80 },
603 { 0x54004, 0x2 },
604 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
605 { 0x54006, LPDDR4_PHY_VREF_VALUE },
606 { 0x54007, 0x0 },
607 { 0x54008, 0x61 },
608 { 0x54009, LPDDR4_HDT_CTL_2D },
609 { 0x5400a, 0x0 },
610 { 0x5400b, 0x2 },
611 { 0x5400c, 0x0 },
612 { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
613 { 0x5400e, 0x0 },
614 { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
615 { 0x54010, LPDDR4_2D_WEIGHT },
616 { 0x54011, 0x0 },
617 { 0x54012, 0x310 },
618 { 0x54013, 0x0 },
619 { 0x54014, 0x0 },
620 { 0x54015, 0x0 },
621 { 0x54016, 0x0 },
622 { 0x54017, 0x0 },
623 { 0x54018, 0x0 },
624 { 0x54019, 0x2dd4 },
625#ifdef WR_POST_EXT_3200
626 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
627#else
628 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
629#endif
630 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
631 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
632 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
633 { 0x5401d, 0x0 },
634 { 0x5401e, LPDDR4_MR22_RANK0 },
635 { 0x5401f, 0x2dd4 },
636#ifdef WR_POST_EXT_3200
637 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
638#else
639 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
640#endif
641 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
642 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
643 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
644 { 0x54023, 0x0 },
645 { 0x54024, LPDDR4_MR22_RANK1 },
646 { 0x54025, 0x0 },
647 { 0x54026, 0x0 },
648 { 0x54027, 0x0 },
649 { 0x54028, 0x0 },
650 { 0x54029, 0x0 },
651 { 0x5402a, 0x0 },
652 { 0x5402b, 0x1000 },
653 { 0x5402c, 0x3 },
654 { 0x5402d, 0x0 },
655 { 0x5402e, 0x0 },
656 { 0x5402f, 0x0 },
657 { 0x54030, 0x0 },
658 { 0x54031, 0x0 },
659
660 { 0x54032, 0xd400 },
661#ifdef WR_POST_EXT_3200
662 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
663#else
664 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
665#endif
666 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
667 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
668 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
669 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
670 { 0x54038, 0xd400 },
671#ifdef WR_POST_EXT_3200
672 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
673#else
674 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
675#endif
676 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
677 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
678 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
679 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
680 { 0x5403e, 0x0 },
681 { 0x5403f, 0x0 },
682 { 0x54040, 0x0 },
683 { 0x54041, 0x0 },
684 { 0x54042, 0x0 },
685 { 0x54043, 0x0 },
686 { 0x54044, 0x0 },
687 { 0xd0000, 0x1 },
688};
689
690/* DRAM PHY init engine image */
691struct dram_cfg_param lpddr4_phy_pie[] = {
692 { 0xd0000, 0x0 },
693 { 0x90000, 0x10 },
694 { 0x90001, 0x400 },
695 { 0x90002, 0x10e },
696 { 0x90003, 0x0 },
697 { 0x90004, 0x0 },
698 { 0x90005, 0x8 },
699 { 0x90029, 0xb },
700 { 0x9002a, 0x480 },
701 { 0x9002b, 0x109 },
702 { 0x9002c, 0x8 },
703 { 0x9002d, 0x448 },
704 { 0x9002e, 0x139 },
705 { 0x9002f, 0x8 },
706 { 0x90030, 0x478 },
707 { 0x90031, 0x109 },
708 { 0x90032, 0x0 },
709 { 0x90033, 0xe8 },
710 { 0x90034, 0x109 },
711 { 0x90035, 0x2 },
712 { 0x90036, 0x10 },
713 { 0x90037, 0x139 },
714 { 0x90038, 0xf },
715 { 0x90039, 0x7c0 },
716 { 0x9003a, 0x139 },
717 { 0x9003b, 0x44 },
718 { 0x9003c, 0x630 },
719 { 0x9003d, 0x159 },
720 { 0x9003e, 0x14f },
721 { 0x9003f, 0x630 },
722 { 0x90040, 0x159 },
723 { 0x90041, 0x47 },
724 { 0x90042, 0x630 },
725 { 0x90043, 0x149 },
726 { 0x90044, 0x4f },
727 { 0x90045, 0x630 },
728 { 0x90046, 0x179 },
729 { 0x90047, 0x8 },
730 { 0x90048, 0xe0 },
731 { 0x90049, 0x109 },
732 { 0x9004a, 0x0 },
733 { 0x9004b, 0x7c8 },
734 { 0x9004c, 0x109 },
735 { 0x9004d, 0x0 },
736 { 0x9004e, 0x1 },
737 { 0x9004f, 0x8 },
738 { 0x90050, 0x0 },
739 { 0x90051, 0x45a },
740 { 0x90052, 0x9 },
741 { 0x90053, 0x0 },
742 { 0x90054, 0x448 },
743 { 0x90055, 0x109 },
744 { 0x90056, 0x40 },
745 { 0x90057, 0x630 },
746 { 0x90058, 0x179 },
747 { 0x90059, 0x1 },
748 { 0x9005a, 0x618 },
749 { 0x9005b, 0x109 },
750 { 0x9005c, 0x40c0 },
751 { 0x9005d, 0x630 },
752 { 0x9005e, 0x149 },
753 { 0x9005f, 0x8 },
754 { 0x90060, 0x4 },
755 { 0x90061, 0x48 },
756 { 0x90062, 0x4040 },
757 { 0x90063, 0x630 },
758 { 0x90064, 0x149 },
759 { 0x90065, 0x0 },
760 { 0x90066, 0x4 },
761 { 0x90067, 0x48 },
762 { 0x90068, 0x40 },
763 { 0x90069, 0x630 },
764 { 0x9006a, 0x149 },
765 { 0x9006b, 0x10 },
766 { 0x9006c, 0x4 },
767 { 0x9006d, 0x18 },
768 { 0x9006e, 0x0 },
769 { 0x9006f, 0x4 },
770 { 0x90070, 0x78 },
771 { 0x90071, 0x549 },
772 { 0x90072, 0x630 },
773 { 0x90073, 0x159 },
774 { 0x90074, 0xd49 },
775 { 0x90075, 0x630 },
776 { 0x90076, 0x159 },
777 { 0x90077, 0x94a },
778 { 0x90078, 0x630 },
779 { 0x90079, 0x159 },
780 { 0x9007a, 0x441 },
781 { 0x9007b, 0x630 },
782 { 0x9007c, 0x149 },
783 { 0x9007d, 0x42 },
784 { 0x9007e, 0x630 },
785 { 0x9007f, 0x149 },
786 { 0x90080, 0x1 },
787 { 0x90081, 0x630 },
788 { 0x90082, 0x149 },
789 { 0x90083, 0x0 },
790 { 0x90084, 0xe0 },
791 { 0x90085, 0x109 },
792 { 0x90086, 0xa },
793 { 0x90087, 0x10 },
794 { 0x90088, 0x109 },
795 { 0x90089, 0x9 },
796 { 0x9008a, 0x3c0 },
797 { 0x9008b, 0x149 },
798 { 0x9008c, 0x9 },
799 { 0x9008d, 0x3c0 },
800 { 0x9008e, 0x159 },
801 { 0x9008f, 0x18 },
802 { 0x90090, 0x10 },
803 { 0x90091, 0x109 },
804 { 0x90092, 0x0 },
805 { 0x90093, 0x3c0 },
806 { 0x90094, 0x109 },
807 { 0x90095, 0x18 },
808 { 0x90096, 0x4 },
809 { 0x90097, 0x48 },
810 { 0x90098, 0x18 },
811 { 0x90099, 0x4 },
812 { 0x9009a, 0x58 },
813 { 0x9009b, 0xa },
814 { 0x9009c, 0x10 },
815 { 0x9009d, 0x109 },
816 { 0x9009e, 0x2 },
817 { 0x9009f, 0x10 },
818 { 0x900a0, 0x109 },
819 { 0x900a1, 0x5 },
820 { 0x900a2, 0x7c0 },
821 { 0x900a3, 0x109 },
822 { 0x900a4, 0x10 },
823 { 0x900a5, 0x10 },
824 { 0x900a6, 0x109 },
825 { 0x40000, 0x811 },
826 { 0x40020, 0x880 },
827 { 0x40040, 0x0 },
828 { 0x40060, 0x0 },
829 { 0x40001, 0x4008 },
830 { 0x40021, 0x83 },
831 { 0x40041, 0x4f },
832 { 0x40061, 0x0 },
833 { 0x40002, 0x4040 },
834 { 0x40022, 0x83 },
835 { 0x40042, 0x51 },
836 { 0x40062, 0x0 },
837 { 0x40003, 0x811 },
838 { 0x40023, 0x880 },
839 { 0x40043, 0x0 },
840 { 0x40063, 0x0 },
841 { 0x40004, 0x720 },
842 { 0x40024, 0xf },
843 { 0x40044, 0x1740 },
844 { 0x40064, 0x0 },
845 { 0x40005, 0x16 },
846 { 0x40025, 0x83 },
847 { 0x40045, 0x4b },
848 { 0x40065, 0x0 },
849 { 0x40006, 0x716 },
850 { 0x40026, 0xf },
851 { 0x40046, 0x2001 },
852 { 0x40066, 0x0 },
853 { 0x40007, 0x716 },
854 { 0x40027, 0xf },
855 { 0x40047, 0x2800 },
856 { 0x40067, 0x0 },
857 { 0x40008, 0x716 },
858 { 0x40028, 0xf },
859 { 0x40048, 0xf00 },
860 { 0x40068, 0x0 },
861 { 0x40009, 0x720 },
862 { 0x40029, 0xf },
863 { 0x40049, 0x1400 },
864 { 0x40069, 0x0 },
865 { 0x4000a, 0xe08 },
866 { 0x4002a, 0xc15 },
867 { 0x4004a, 0x0 },
868 { 0x4006a, 0x0 },
869 { 0x4000b, 0x623 },
870 { 0x4002b, 0x15 },
871 { 0x4004b, 0x0 },
872 { 0x4006b, 0x0 },
873 { 0x4000c, 0x4028 },
874 { 0x4002c, 0x80 },
875 { 0x4004c, 0x0 },
876 { 0x4006c, 0x0 },
877 { 0x4000d, 0xe08 },
878 { 0x4002d, 0xc1a },
879 { 0x4004d, 0x0 },
880 { 0x4006d, 0x0 },
881 { 0x4000e, 0x623 },
882 { 0x4002e, 0x1a },
883 { 0x4004e, 0x0 },
884 { 0x4006e, 0x0 },
885 { 0x4000f, 0x4040 },
886 { 0x4002f, 0x80 },
887 { 0x4004f, 0x0 },
888 { 0x4006f, 0x0 },
889 { 0x40010, 0x2604 },
890 { 0x40030, 0x15 },
891 { 0x40050, 0x0 },
892 { 0x40070, 0x0 },
893 { 0x40011, 0x708 },
894 { 0x40031, 0x5 },
895 { 0x40051, 0x0 },
896 { 0x40071, 0x2002 },
897 { 0x40012, 0x8 },
898 { 0x40032, 0x80 },
899 { 0x40052, 0x0 },
900 { 0x40072, 0x0 },
901 { 0x40013, 0x2604 },
902 { 0x40033, 0x1a },
903 { 0x40053, 0x0 },
904 { 0x40073, 0x0 },
905 { 0x40014, 0x708 },
906 { 0x40034, 0xa },
907 { 0x40054, 0x0 },
908 { 0x40074, 0x2002 },
909 { 0x40015, 0x4040 },
910 { 0x40035, 0x80 },
911 { 0x40055, 0x0 },
912 { 0x40075, 0x0 },
913 { 0x40016, 0x60a },
914 { 0x40036, 0x15 },
915 { 0x40056, 0x1200 },
916 { 0x40076, 0x0 },
917 { 0x40017, 0x61a },
918 { 0x40037, 0x15 },
919 { 0x40057, 0x1300 },
920 { 0x40077, 0x0 },
921 { 0x40018, 0x60a },
922 { 0x40038, 0x1a },
923 { 0x40058, 0x1200 },
924 { 0x40078, 0x0 },
925 { 0x40019, 0x642 },
926 { 0x40039, 0x1a },
927 { 0x40059, 0x1300 },
928 { 0x40079, 0x0 },
929 { 0x4001a, 0x4808 },
930 { 0x4003a, 0x880 },
931 { 0x4005a, 0x0 },
932 { 0x4007a, 0x0 },
933 { 0x900a7, 0x0 },
934 { 0x900a8, 0x790 },
935 { 0x900a9, 0x11a },
936 { 0x900aa, 0x8 },
937 { 0x900ab, 0x7aa },
938 { 0x900ac, 0x2a },
939 { 0x900ad, 0x10 },
940 { 0x900ae, 0x7b2 },
941 { 0x900af, 0x2a },
942 { 0x900b0, 0x0 },
943 { 0x900b1, 0x7c8 },
944 { 0x900b2, 0x109 },
945 { 0x900b3, 0x10 },
946 { 0x900b4, 0x2a8 },
947 { 0x900b5, 0x129 },
948 { 0x900b6, 0x8 },
949 { 0x900b7, 0x370 },
950 { 0x900b8, 0x129 },
951 { 0x900b9, 0xa },
952 { 0x900ba, 0x3c8 },
953 { 0x900bb, 0x1a9 },
954 { 0x900bc, 0xc },
955 { 0x900bd, 0x408 },
956 { 0x900be, 0x199 },
957 { 0x900bf, 0x14 },
958 { 0x900c0, 0x790 },
959 { 0x900c1, 0x11a },
960 { 0x900c2, 0x8 },
961 { 0x900c3, 0x4 },
962 { 0x900c4, 0x18 },
963 { 0x900c5, 0xe },
964 { 0x900c6, 0x408 },
965 { 0x900c7, 0x199 },
966 { 0x900c8, 0x8 },
967 { 0x900c9, 0x8568 },
968 { 0x900ca, 0x108 },
969 { 0x900cb, 0x18 },
970 { 0x900cc, 0x790 },
971 { 0x900cd, 0x16a },
972 { 0x900ce, 0x8 },
973 { 0x900cf, 0x1d8 },
974 { 0x900d0, 0x169 },
975 { 0x900d1, 0x10 },
976 { 0x900d2, 0x8558 },
977 { 0x900d3, 0x168 },
978 { 0x900d4, 0x70 },
979 { 0x900d5, 0x788 },
980 { 0x900d6, 0x16a },
981 { 0x900d7, 0x1ff8 },
982 { 0x900d8, 0x85a8 },
983 { 0x900d9, 0x1e8 },
984 { 0x900da, 0x50 },
985 { 0x900db, 0x798 },
986 { 0x900dc, 0x16a },
987 { 0x900dd, 0x60 },
988 { 0x900de, 0x7a0 },
989 { 0x900df, 0x16a },
990 { 0x900e0, 0x8 },
991 { 0x900e1, 0x8310 },
992 { 0x900e2, 0x168 },
993 { 0x900e3, 0x8 },
994 { 0x900e4, 0xa310 },
995 { 0x900e5, 0x168 },
996 { 0x900e6, 0xa },
997 { 0x900e7, 0x408 },
998 { 0x900e8, 0x169 },
999 { 0x900e9, 0x6e },
1000 { 0x900ea, 0x0 },
1001 { 0x900eb, 0x68 },
1002 { 0x900ec, 0x0 },
1003 { 0x900ed, 0x408 },
1004 { 0x900ee, 0x169 },
1005 { 0x900ef, 0x0 },
1006 { 0x900f0, 0x8310 },
1007 { 0x900f1, 0x168 },
1008 { 0x900f2, 0x0 },
1009 { 0x900f3, 0xa310 },
1010 { 0x900f4, 0x168 },
1011 { 0x900f5, 0x1ff8 },
1012 { 0x900f6, 0x85a8 },
1013 { 0x900f7, 0x1e8 },
1014 { 0x900f8, 0x68 },
1015 { 0x900f9, 0x798 },
1016 { 0x900fa, 0x16a },
1017 { 0x900fb, 0x78 },
1018 { 0x900fc, 0x7a0 },
1019 { 0x900fd, 0x16a },
1020 { 0x900fe, 0x68 },
1021 { 0x900ff, 0x790 },
1022 { 0x90100, 0x16a },
1023 { 0x90101, 0x8 },
1024 { 0x90102, 0x8b10 },
1025 { 0x90103, 0x168 },
1026 { 0x90104, 0x8 },
1027 { 0x90105, 0xab10 },
1028 { 0x90106, 0x168 },
1029 { 0x90107, 0xa },
1030 { 0x90108, 0x408 },
1031 { 0x90109, 0x169 },
1032 { 0x9010a, 0x58 },
1033 { 0x9010b, 0x0 },
1034 { 0x9010c, 0x68 },
1035 { 0x9010d, 0x0 },
1036 { 0x9010e, 0x408 },
1037 { 0x9010f, 0x169 },
1038 { 0x90110, 0x0 },
1039 { 0x90111, 0x8b10 },
1040 { 0x90112, 0x168 },
1041 { 0x90113, 0x0 },
1042 { 0x90114, 0xab10 },
1043 { 0x90115, 0x168 },
1044 { 0x90116, 0x0 },
1045 { 0x90117, 0x1d8 },
1046 { 0x90118, 0x169 },
1047 { 0x90119, 0x80 },
1048 { 0x9011a, 0x790 },
1049 { 0x9011b, 0x16a },
1050 { 0x9011c, 0x18 },
1051 { 0x9011d, 0x7aa },
1052 { 0x9011e, 0x6a },
1053 { 0x9011f, 0xa },
1054 { 0x90120, 0x0 },
1055 { 0x90121, 0x1e9 },
1056 { 0x90122, 0x8 },
1057 { 0x90123, 0x8080 },
1058 { 0x90124, 0x108 },
1059 { 0x90125, 0xf },
1060 { 0x90126, 0x408 },
1061 { 0x90127, 0x169 },
1062 { 0x90128, 0xc },
1063 { 0x90129, 0x0 },
1064 { 0x9012a, 0x68 },
1065 { 0x9012b, 0x9 },
1066 { 0x9012c, 0x0 },
1067 { 0x9012d, 0x1a9 },
1068 { 0x9012e, 0x0 },
1069 { 0x9012f, 0x408 },
1070 { 0x90130, 0x169 },
1071 { 0x90131, 0x0 },
1072 { 0x90132, 0x8080 },
1073 { 0x90133, 0x108 },
1074 { 0x90134, 0x8 },
1075 { 0x90135, 0x7aa },
1076 { 0x90136, 0x6a },
1077 { 0x90137, 0x0 },
1078 { 0x90138, 0x8568 },
1079 { 0x90139, 0x108 },
1080 { 0x9013a, 0xb7 },
1081 { 0x9013b, 0x790 },
1082 { 0x9013c, 0x16a },
1083 { 0x9013d, 0x1f },
1084 { 0x9013e, 0x0 },
1085 { 0x9013f, 0x68 },
1086 { 0x90140, 0x8 },
1087 { 0x90141, 0x8558 },
1088 { 0x90142, 0x168 },
1089 { 0x90143, 0xf },
1090 { 0x90144, 0x408 },
1091 { 0x90145, 0x169 },
1092 { 0x90146, 0xc },
1093 { 0x90147, 0x0 },
1094 { 0x90148, 0x68 },
1095 { 0x90149, 0x0 },
1096 { 0x9014a, 0x408 },
1097 { 0x9014b, 0x169 },
1098 { 0x9014c, 0x0 },
1099 { 0x9014d, 0x8558 },
1100 { 0x9014e, 0x168 },
1101 { 0x9014f, 0x8 },
1102 { 0x90150, 0x3c8 },
1103 { 0x90151, 0x1a9 },
1104 { 0x90152, 0x3 },
1105 { 0x90153, 0x370 },
1106 { 0x90154, 0x129 },
1107 { 0x90155, 0x20 },
1108 { 0x90156, 0x2aa },
1109 { 0x90157, 0x9 },
1110 { 0x90158, 0x0 },
1111 { 0x90159, 0x400 },
1112 { 0x9015a, 0x10e },
1113 { 0x9015b, 0x8 },
1114 { 0x9015c, 0xe8 },
1115 { 0x9015d, 0x109 },
1116 { 0x9015e, 0x0 },
1117 { 0x9015f, 0x8140 },
1118 { 0x90160, 0x10c },
1119 { 0x90161, 0x10 },
1120 { 0x90162, 0x8138 },
1121 { 0x90163, 0x10c },
1122 { 0x90164, 0x8 },
1123 { 0x90165, 0x7c8 },
1124 { 0x90166, 0x101 },
1125 { 0x90167, 0x8 },
1126 { 0x90168, 0x0 },
1127 { 0x90169, 0x8 },
1128 { 0x9016a, 0x8 },
1129 { 0x9016b, 0x448 },
1130 { 0x9016c, 0x109 },
1131 { 0x9016d, 0xf },
1132 { 0x9016e, 0x7c0 },
1133 { 0x9016f, 0x109 },
1134 { 0x90170, 0x0 },
1135 { 0x90171, 0xe8 },
1136 { 0x90172, 0x109 },
1137 { 0x90173, 0x47 },
1138 { 0x90174, 0x630 },
1139 { 0x90175, 0x109 },
1140 { 0x90176, 0x8 },
1141 { 0x90177, 0x618 },
1142 { 0x90178, 0x109 },
1143 { 0x90179, 0x8 },
1144 { 0x9017a, 0xe0 },
1145 { 0x9017b, 0x109 },
1146 { 0x9017c, 0x0 },
1147 { 0x9017d, 0x7c8 },
1148 { 0x9017e, 0x109 },
1149 { 0x9017f, 0x8 },
1150 { 0x90180, 0x8140 },
1151 { 0x90181, 0x10c },
1152 { 0x90182, 0x0 },
1153 { 0x90183, 0x1 },
1154 { 0x90184, 0x8 },
1155 { 0x90185, 0x8 },
1156 { 0x90186, 0x4 },
1157 { 0x90187, 0x8 },
1158 { 0x90188, 0x8 },
1159 { 0x90189, 0x7c8 },
1160 { 0x9018a, 0x101 },
1161 { 0x90006, 0x0 },
1162 { 0x90007, 0x0 },
1163 { 0x90008, 0x8 },
1164 { 0x90009, 0x0 },
1165 { 0x9000a, 0x0 },
1166 { 0x9000b, 0x0 },
1167 { 0xd00e7, 0x400 },
1168 { 0x90017, 0x0 },
1169 { 0x9001f, 0x2a },
1170 { 0x90026, 0x6a },
1171 { 0x400d0, 0x0 },
1172 { 0x400d1, 0x101 },
1173 { 0x400d2, 0x105 },
1174 { 0x400d3, 0x107 },
1175 { 0x400d4, 0x10f },
1176 { 0x400d5, 0x202 },
1177 { 0x400d6, 0x20a },
1178 { 0x400d7, 0x20b },
1179 { 0x2003a, 0x2 },
1180 { 0x2000b, 0x64 },
1181 { 0x2000c, 0xc8 },
1182 { 0x2000d, 0x7d0 },
1183 { 0x2000e, 0x2c },
1184 { 0x12000b, 0xc },
1185 { 0x12000c, 0x19 },
1186 { 0x12000d, 0xfa },
1187 { 0x12000e, 0x10 },
1188 { 0x22000b, 0x3 },
1189 { 0x22000c, 0x6 },
1190 { 0x22000d, 0x3e },
1191 { 0x22000e, 0x10 },
1192 { 0x9000c, 0x0 },
1193 { 0x9000d, 0x173 },
1194 { 0x9000e, 0x60 },
1195 { 0x9000f, 0x6110 },
1196 { 0x90010, 0x2152 },
1197 { 0x90011, 0xdfbd },
1198 { 0x90012, 0x60 },
1199 { 0x90013, 0x6152 },
1200 { 0x20010, 0x5a },
1201 { 0x20011, 0x3 },
1202 { 0x40080, 0xe0 },
1203 { 0x40081, 0x12 },
1204 { 0x40082, 0xe0 },
1205 { 0x40083, 0x12 },
1206 { 0x40084, 0xe0 },
1207 { 0x40085, 0x12 },
1208 { 0x140080, 0xe0 },
1209 { 0x140081, 0x12 },
1210 { 0x140082, 0xe0 },
1211 { 0x140083, 0x12 },
1212 { 0x140084, 0xe0 },
1213 { 0x140085, 0x12 },
1214 { 0x240080, 0xe0 },
1215 { 0x240081, 0x12 },
1216 { 0x240082, 0xe0 },
1217 { 0x240083, 0x12 },
1218 { 0x240084, 0xe0 },
1219 { 0x240085, 0x12 },
1220 { 0x400fd, 0xf },
1221 { 0x10011, 0x1 },
1222 { 0x10012, 0x1 },
1223 { 0x10013, 0x180 },
1224 { 0x10018, 0x1 },
1225 { 0x10002, 0x6209 },
1226 { 0x100b2, 0x1 },
1227 { 0x101b4, 0x1 },
1228 { 0x102b4, 0x1 },
1229 { 0x103b4, 0x1 },
1230 { 0x104b4, 0x1 },
1231 { 0x105b4, 0x1 },
1232 { 0x106b4, 0x1 },
1233 { 0x107b4, 0x1 },
1234 { 0x108b4, 0x1 },
1235 { 0x11011, 0x1 },
1236 { 0x11012, 0x1 },
1237 { 0x11013, 0x180 },
1238 { 0x11018, 0x1 },
1239 { 0x11002, 0x6209 },
1240 { 0x110b2, 0x1 },
1241 { 0x111b4, 0x1 },
1242 { 0x112b4, 0x1 },
1243 { 0x113b4, 0x1 },
1244 { 0x114b4, 0x1 },
1245 { 0x115b4, 0x1 },
1246 { 0x116b4, 0x1 },
1247 { 0x117b4, 0x1 },
1248 { 0x118b4, 0x1 },
1249 { 0x12011, 0x1 },
1250 { 0x12012, 0x1 },
1251 { 0x12013, 0x180 },
1252 { 0x12018, 0x1 },
1253 { 0x12002, 0x6209 },
1254 { 0x120b2, 0x1 },
1255 { 0x121b4, 0x1 },
1256 { 0x122b4, 0x1 },
1257 { 0x123b4, 0x1 },
1258 { 0x124b4, 0x1 },
1259 { 0x125b4, 0x1 },
1260 { 0x126b4, 0x1 },
1261 { 0x127b4, 0x1 },
1262 { 0x128b4, 0x1 },
1263 { 0x13011, 0x1 },
1264 { 0x13012, 0x1 },
1265 { 0x13013, 0x180 },
1266 { 0x13018, 0x1 },
1267 { 0x13002, 0x6209 },
1268 { 0x130b2, 0x1 },
1269 { 0x131b4, 0x1 },
1270 { 0x132b4, 0x1 },
1271 { 0x133b4, 0x1 },
1272 { 0x134b4, 0x1 },
1273 { 0x135b4, 0x1 },
1274 { 0x136b4, 0x1 },
1275 { 0x137b4, 0x1 },
1276 { 0x138b4, 0x1 },
1277 { 0x2003a, 0x2 },
1278 { 0xc0080, 0x2 },
1279 { 0xd0000, 0x1 },
1280};
1281
1282struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1283 {
1284 /* P0 3200mts 1D */
1285 .drate = 3200,
1286 .fw_type = FW_1D_IMAGE,
1287 .fsp_cfg = lpddr4_fsp0_cfg,
1288 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1289 },
1290 {
1291 /* P1 400mts 1D */
1292 .drate = 400,
1293 .fw_type = FW_1D_IMAGE,
1294 .fsp_cfg = lpddr4_fsp1_cfg,
1295 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1296 },
1297 {
1298 /* P1 100mts 1D */
1299 .drate = 100,
1300 .fw_type = FW_1D_IMAGE,
1301 .fsp_cfg = lpddr4_fsp2_cfg,
1302 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
1303 },
1304 {
1305 /* P0 3200mts 2D */
1306 .drate = 3200,
1307 .fw_type = FW_2D_IMAGE,
1308 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1309 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1310 },
1311};
1312
1313/* lpddr4 timing config params on EVK board */
1314struct dram_timing_info dram_timing = {
1315 .ddrc_cfg = lpddr4_ddrc_cfg,
1316 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1317 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1318 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1319 .fsp_msg = lpddr4_dram_fsp_msg,
1320 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1321 .ddrphy_pie = lpddr4_phy_pie,
1322 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1323 .fsp_table = { 3200, 400, 100, },
1324};