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Lukasz Majewskicd457c42019-06-24 15:50:41 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 *
6 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
8 */
9#ifndef __LINUX_CLK_PROVIDER_H
10#define __LINUX_CLK_PROVIDER_H
11
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020012static inline void clk_dm(ulong id, struct clk *clk)
13{
14 if (!IS_ERR(clk))
15 clk->id = id;
16}
17
18/*
19 * flags used across common struct clk. these flags should only affect the
20 * top-level framework. custom flags for dealing with hardware specifics
21 * belong in struct clk_foo
22 *
23 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
24 */
25#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
26#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
27#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
28#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
29 /* unused */
30#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
31#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
32#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
34#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
35#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
36#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
37/* parents need enable during gate/ungate, set rate and re-parent */
38#define CLK_OPS_PARENT_ENABLE BIT(12)
39/* duty cycle call may be forwarded to the parent clock */
40#define CLK_DUTY_CYCLE_PARENT BIT(13)
41
42#define CLK_MUX_INDEX_ONE BIT(0)
43#define CLK_MUX_INDEX_BIT BIT(1)
44#define CLK_MUX_HIWORD_MASK BIT(2)
45#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
46#define CLK_MUX_ROUND_CLOSEST BIT(4)
47
48struct clk_mux {
49 struct clk clk;
50 void __iomem *reg;
51 u32 *table;
52 u32 mask;
53 u8 shift;
54 u8 flags;
55
56 /*
57 * Fields from struct clk_init_data - this struct has been
58 * omitted to avoid too deep level of CCF for bootloader
59 */
60 const char * const *parent_names;
61 u8 num_parents;
Lukasz Majewski669b7732019-06-24 15:50:49 +020062#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
63 u32 io_mux_val;
64#endif
65
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020066};
67
68#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
69
70struct clk_div_table {
71 unsigned int val;
72 unsigned int div;
73};
74
75struct clk_divider {
76 struct clk clk;
77 void __iomem *reg;
78 u8 shift;
79 u8 width;
80 u8 flags;
81 const struct clk_div_table *table;
Lukasz Majewskibb18f1b2019-06-24 15:50:48 +020082#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
83 u32 io_divider_val;
84#endif
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020085};
86
87#define clk_div_mask(width) ((1 << (width)) - 1)
88#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
89
90#define CLK_DIVIDER_ONE_BASED BIT(0)
91#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
92#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
93#define CLK_DIVIDER_HIWORD_MASK BIT(3)
94#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
95#define CLK_DIVIDER_READ_ONLY BIT(5)
96#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
97
98struct clk_fixed_factor {
99 struct clk clk;
100 unsigned int mult;
101 unsigned int div;
102};
103
104#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
105 clk)
106
107int clk_register(struct clk *clk, const char *drv_name, const char *name,
108 const char *parent_name);
109
110struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
111 const char *parent_name, unsigned long flags,
112 unsigned int mult, unsigned int div);
113
114struct clk *clk_register_divider(struct device *dev, const char *name,
115 const char *parent_name, unsigned long flags,
116 void __iomem *reg, u8 shift, u8 width,
117 u8 clk_divider_flags);
118
119struct clk *clk_register_mux(struct device *dev, const char *name,
120 const char * const *parent_names, u8 num_parents,
121 unsigned long flags,
122 void __iomem *reg, u8 shift, u8 width,
123 u8 clk_mux_flags);
124
125const char *clk_hw_get_name(const struct clk *hw);
126ulong clk_generic_get_rate(struct clk *clk);
127
Lukasz Majewskicd457c42019-06-24 15:50:41 +0200128static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
129{
130 return (struct clk *)dev_get_uclass_priv(dev);
131}
132#endif /* __LINUX_CLK_PROVIDER_H */