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Paul Kocialkowskif4865f52015-08-04 17:04:07 +02001#
2# MUSB Controller Driver
3#
4comment "MUSB Controller Driver"
5
6config USB_MUSB_HOST
7 bool "MUSB host mode support"
8 help
9 Enables the MUSB USB dual-role controller in host mode.
10
11config USB_MUSB_GADGET
12 bool "MUSB gadget mode support"
Sam Protsenkob4a0bf72016-04-13 14:20:25 +030013 select USB_GADGET_DUALSPEED
Paul Kocialkowskif4865f52015-08-04 17:04:07 +020014 help
15 Enables the MUSB USB dual-role controller in gadget mode.
Paul Kocialkowskie16ab872015-08-04 17:04:08 +020016
Mugunthan V N5b5479c2016-11-17 14:38:08 +053017config USB_MUSB_TI
18 bool "Enable TI OTG USB controller"
19 depends on DM_USB
20 default n
21 help
22 Say y here to enable support for the dual role high
23 speed USB controller based on the Mentor Graphics
24 silicon IP.
25
Adam Ford9d3e6c32017-12-29 08:16:05 -060026config USB_MUSB_OMAP2PLUS
27 tristate "OMAP2430 and onwards"
28 depends on ARCH_OMAP2PLUS
29
30config USB_MUSB_AM35X
31 bool "AM35x"
32
33config USB_MUSB_DSPS
34 bool "TI DSPS platforms"
35
Paul Kocialkowskie16ab872015-08-04 17:04:08 +020036if USB_MUSB_HOST || USB_MUSB_GADGET
37
Purna Chandra Mandal05bc3f42016-03-21 13:05:42 +053038config USB_MUSB_PIC32
39 bool "Enable Microchip PIC32 DRC USB controller"
40 depends on DM_USB && MACH_PIC32
41 help
42 Say y to enable PIC32 USB DRC controller support
43 if it is available on your Microchip PIC32 platform.
44
Paul Kocialkowskie16ab872015-08-04 17:04:08 +020045config USB_MUSB_SUNXI
46 bool "Enable sunxi OTG / DRC USB controller"
47 depends on ARCH_SUNXI
48 default y
49 ---help---
50 Say y here to enable support for the sunxi OTG / DRC USB controller
Hans de Goededa6c37b2015-08-16 11:15:29 +020051 used on almost all sunxi boards.
Paul Kocialkowskie16ab872015-08-04 17:04:08 +020052
53endif
Adam Ford9d3e6c32017-12-29 08:16:05 -060054
55config USB_MUSB_PIO_ONLY
56 bool "Disable DMA (always use PIO)"
57 default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS || USB_MUSB_DSPS || USB_MUSB_SUNXI
58 help
59 All data is copied between memory and FIFO by the CPU.
60 DMA controllers are ignored.