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Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -07001/*
2 * Aeronix Zipit Z2 configuration file
3 *
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
15#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16#define CONFIG_SYS_TEXT_BASE 0x0
17
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070018#undef CONFIG_SKIP_LOWLEVEL_INIT
19#define CONFIG_PREBOOT
20
21/*
22 * Environment settings
23 */
24#define CONFIG_ENV_OVERWRITE
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070025#define CONFIG_ENV_ADDR 0x40000
26#define CONFIG_ENV_SIZE 0x10000
27
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070028#define CONFIG_SYS_MALLOC_LEN (128*1024)
29#define CONFIG_ARCH_CPU_INIT
30
31#define CONFIG_BOOTCOMMAND \
32 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
33 "then " \
34 "source 0xa0000000; " \
35 "else " \
36 "bootm 0x50000; " \
37 "fi; "
38#define CONFIG_BOOTARGS \
39 "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
40#define CONFIG_TIMESTAMP
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070041#define CONFIG_CMDLINE_TAG
42#define CONFIG_SETUP_MEMORY_TAGS
43#define CONFIG_SYS_TEXT_BASE 0x0
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070044
45/*
46 * Serial Console Configuration
47 * STUART - the lower serial port on Colibri board
48 */
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070049#define CONFIG_STUART 1
50#define CONFIG_CONS_INDEX 2
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070051
52/*
53 * Bootloader Components Configuration
54 */
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070055
56/*
57 * MMC Card Configuration
58 */
59#ifdef CONFIG_CMD_MMC
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070060#define CONFIG_PXA_MMC_GENERIC
61#define CONFIG_SYS_MMC_BASE 0xF0000000
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070062#endif
63
64/*
65 * SPI and LCD
66 */
67#ifdef CONFIG_CMD_SPI
68#define CONFIG_SOFT_SPI
Vasily Khoruzhickbf81f202016-03-20 18:37:01 -070069#define CONFIG_LCD_ROTATION
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070070#define CONFIG_PXA_LCD
71#define CONFIG_LMS283GF05
72
73#define SPI_DELAY udelay(10)
74#define SPI_SDA(val) zipitz2_spi_sda(val)
75#define SPI_SCL(val) zipitz2_spi_scl(val)
76#define SPI_READ zipitz2_spi_read()
77#ifndef __ASSEMBLY__
78void zipitz2_spi_sda(int);
79void zipitz2_spi_scl(int);
80unsigned char zipitz2_spi_read(void);
81#endif
82#endif
83
Vasily Khoruzhicka2cbff02016-03-20 18:37:00 -070084#define CONFIG_SYS_LONGHELP /* undef to save memory */
85#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
86#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
87#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
88#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
89#define CONFIG_SYS_DEVICE_NULLDEV 1
90
91/*
92 * Clock Configuration
93 */
94#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
95
96/*
97 * SRAM Map
98 */
99#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
100#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
101
102/*
103 * DRAM Map
104 */
105#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
106#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
107#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
108
109#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
110#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
111
112#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
113#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
114
115#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
116
117#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
118#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
119
120/*
121 * NOR FLASH
122 */
123#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
124#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
125#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
126#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
127
128#define CONFIG_SYS_FLASH_CFI
129#define CONFIG_FLASH_CFI_DRIVER 1
130#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
131
132#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
133#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
134
135#define CONFIG_SYS_MAX_FLASH_BANKS 1
136#define CONFIG_SYS_MAX_FLASH_SECT 256
137
138#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
139
140#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
141#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
142#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
143#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
144#define CONFIG_SYS_FLASH_PROTECTION
145
146/*
147 * GPIO settings
148 */
149#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
150#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
151#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
152#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
153#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
154#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
155#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
156#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
157#define CONFIG_SYS_GPCR0_VAL 0x00000000
158#define CONFIG_SYS_GPCR1_VAL 0x00000020
159#define CONFIG_SYS_GPCR2_VAL 0x00000000
160#define CONFIG_SYS_GPCR3_VAL 0x00000000
161#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
162#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
163#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
164#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
165#define CONFIG_SYS_GPSR0_VAL 0x06080400
166#define CONFIG_SYS_GPSR1_VAL 0x007f0000
167#define CONFIG_SYS_GPSR2_VAL 0x032a0000
168#define CONFIG_SYS_GPSR3_VAL 0x00000180
169
170#define CONFIG_SYS_PSSR_VAL 0x30
171
172/*
173 * Clock settings
174 */
175#define CONFIG_SYS_CKEN 0x00511220
176#define CONFIG_SYS_CCCR 0x00000190
177
178/*
179 * Memory settings
180 */
181#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
182#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
183#define CONFIG_SYS_MSC2_VAL 0x0000b884
184#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
185#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
186#define CONFIG_SYS_MDMRS_VAL 0x00000000
187#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
188#define CONFIG_SYS_SXCNFG_VAL 0x40044004
189
190/*
191 * PCMCIA and CF Interfaces
192 */
193#define CONFIG_SYS_MECR_VAL 0x00000001
194#define CONFIG_SYS_MCMEM0_VAL 0x00014307
195#define CONFIG_SYS_MCMEM1_VAL 0x00014307
196#define CONFIG_SYS_MCATT0_VAL 0x0001c787
197#define CONFIG_SYS_MCATT1_VAL 0x0001c787
198#define CONFIG_SYS_MCIO0_VAL 0x0001430f
199#define CONFIG_SYS_MCIO1_VAL 0x0001430f
200
201#include "pxa-common.h"
202
203#endif /* __CONFIG_H */