Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007-2008 |
Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 3 | * Stelian Pop <stelian@popies.net> |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 4 | * Lead Tech Design <www.leadtechdesign.com> |
| 5 | * |
| 6 | * Configuation settings for the AT91SAM9RLEK board. |
| 7 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 14 | #include <asm/hardware.h> |
| 15 | |
| 16 | #define CONFIG_SYS_TEXT_BASE 0x21F00000 |
Jens Scharsig | 128ecd0 | 2010-02-03 22:45:42 +0100 | [diff] [blame] | 17 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 18 | /* ARM asynchronous clock */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 19 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 20 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 21 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 22 | #define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */ |
| 23 | |
Jean-Christophe PLAGNIOL-VILLARD | 23164f1 | 2009-04-16 21:30:44 +0200 | [diff] [blame] | 24 | #define CONFIG_ARCH_CPU_INIT |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 25 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 26 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 27 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 28 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 29 | #define CONFIG_INITRD_TAG 1 |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 30 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 31 | #define CONFIG_ATMEL_LEGACY |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * Hardware drivers |
| 35 | */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 36 | |
Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 37 | /* LCD */ |
Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 38 | #define LCD_BPP LCD_COLOR8 |
| 39 | #define CONFIG_LCD_LOGO 1 |
| 40 | #undef LCD_TEST_PATTERN |
| 41 | #define CONFIG_LCD_INFO 1 |
| 42 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 |
Stelian Pop | cea5c53 | 2008-05-08 14:52:32 +0200 | [diff] [blame] | 43 | #define CONFIG_ATMEL_LCD 1 |
| 44 | #define CONFIG_ATMEL_LCD_RGB565 1 |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 45 | /* Let board_init_f handle the framebuffer allocation */ |
| 46 | #undef CONFIG_FB_ADDR |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 47 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 48 | /* SDRAM */ |
| 49 | #define CONFIG_NR_DRAM_BANKS 1 |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 50 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 51 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 52 | |
| 53 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | 3cbbeb1 | 2017-04-18 15:28:27 +0800 | [diff] [blame] | 54 | (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 55 | |
| 56 | /* DataFlash */ |
Jean-Christophe PLAGNIOL-VILLARD | e5437ac | 2009-03-27 23:26:44 +0100 | [diff] [blame] | 57 | #define CONFIG_ATMEL_DATAFLASH_SPI |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 58 | #define CONFIG_HAS_DATAFLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 |
| 60 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 61 | #define AT91_SPI_CLK 15000000 |
| 62 | #define DATAFLASH_TCSS (0x1a << 16) |
| 63 | #define DATAFLASH_TCHS (0x1 << 24) |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 64 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 65 | /* NAND flash */ |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 66 | #ifdef CONFIG_CMD_NAND |
| 67 | #define CONFIG_NAND_ATMEL |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 69 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 70 | #define CONFIG_SYS_NAND_DBW_8 1 |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 71 | /* our ALE is AD21 */ |
| 72 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 73 | /* our CLE is AD22 */ |
| 74 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 75 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 |
| 76 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17 |
Wolfgang Denk | 1f79774 | 2009-07-18 21:52:24 +0200 | [diff] [blame] | 77 | |
Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 78 | #endif |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 79 | |
| 80 | /* Ethernet - not present */ |
| 81 | |
| 82 | /* USB - not supported */ |
| 83 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 85 | |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 86 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 88 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #ifdef CONFIG_SYS_USE_DATAFLASH |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 90 | |
| 91 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 93 | #define CONFIG_ENV_OFFSET 0x4200 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 95 | #define CONFIG_ENV_SIZE 0x4200 |
Alexandre Belloni | 9ef19ba | 2012-07-02 04:26:58 +0000 | [diff] [blame] | 96 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 97 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
| 98 | "root=/dev/mtdblock0 " \ |
Albin Tonnerre | eaa6db2 | 2009-07-22 18:30:03 +0200 | [diff] [blame] | 99 | "mtdparts=atmel_nand:-(root) "\ |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 100 | "rw rootfstype=jffs2" |
| 101 | |
Wu, Josh | 7ff194f | 2015-02-02 17:51:01 +0800 | [diff] [blame] | 102 | #elif CONFIG_SYS_USE_NANDFLASH |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 103 | |
| 104 | /* bootstrap + u-boot + env + linux in nandflash */ |
Wenyou Yang | 3cbbeb1 | 2017-04-18 15:28:27 +0800 | [diff] [blame] | 105 | #define CONFIG_ENV_OFFSET 0x120000 |
Wu, Josh | f8e70d9 | 2015-02-03 11:38:30 +0800 | [diff] [blame] | 106 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 107 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
Wu, Josh | f8e70d9 | 2015-02-03 11:38:30 +0800 | [diff] [blame] | 108 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \ |
| 109 | "nand read 0x21000000 0x180000 0x80000; " \ |
| 110 | "bootz 0x22000000 - 0x21000000" |
| 111 | #define CONFIG_BOOTARGS \ |
| 112 | "console=ttyS0,115200 earlyprintk " \ |
| 113 | "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ |
Robert P. J. Day | a7e1f50 | 2016-09-01 09:49:14 -0400 | [diff] [blame] | 114 | "256K(env),256k(env_redundant),256k(spare)," \ |
Wu, Josh | f8e70d9 | 2015-02-03 11:38:30 +0800 | [diff] [blame] | 115 | "512k(dtb),6M(kernel)ro,-(rootfs) " \ |
| 116 | "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 117 | |
Wu, Josh | 7ff194f | 2015-02-02 17:51:01 +0800 | [diff] [blame] | 118 | #else /* CONFIG_SYS_USE_MMC */ |
| 119 | |
| 120 | /* bootstrap + u-boot + env + linux in mmc */ |
Wu, Josh | 7ff194f | 2015-02-02 17:51:01 +0800 | [diff] [blame] | 121 | #define CONFIG_ENV_SIZE 0x4000 |
| 122 | #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \ |
| 123 | "fatload mmc 0:1 0x22000000 zImage; " \ |
| 124 | "bootz 0x22000000 - 0x21000000" |
| 125 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
| 126 | "mtdparts=atmel_nand:" \ |
| 127 | "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ |
| 128 | "root=/dev/mmcblk0p2 rw rootwait" |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 129 | #endif |
| 130 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_CBSIZE 256 |
| 132 | #define CONFIG_SYS_MAXARGS 16 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_LONGHELP 1 |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 134 | #define CONFIG_CMDLINE_EDITING 1 |
Alexandre Belloni | 9ef19ba | 2012-07-02 04:26:58 +0000 | [diff] [blame] | 135 | #define CONFIG_AUTO_COMPLETE |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 136 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 137 | /* |
| 138 | * Size of malloc() pool |
| 139 | */ |
Xu, Hong | 0c0fb21 | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 140 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 141 | |
Stelian Pop | 0bf5cad | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 142 | #endif |