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Tom Rix330a90a2009-06-28 12:52:29 -05001/*
2 * Copyright (c) 2009 Wind River Systems, Inc.
3 * Tom Rix <Tom.Rix at windriver.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Rix330a90a2009-06-28 12:52:29 -05006 *
Tom Rix0f2a8042009-06-28 12:52:30 -05007 * twl4030_power_reset_init is derived from code on omapzoom,
8 * git://git.omapzoom.com/repo/u-boot.git
Tom Rix330a90a2009-06-28 12:52:29 -05009 *
10 * Copyright (C) 2007-2009 Texas Instruments, Inc.
Tom Rix0f2a8042009-06-28 12:52:30 -050011 *
12 * twl4030_power_init is from cpu/omap3/common.c, power_init_r
13 *
14 * (C) Copyright 2004-2008
15 * Texas Instruments, <www.ti.com>
16 *
17 * Author :
18 * Sunil Kumar <sunilsaini05 at gmail.com>
19 * Shashi Ranjan <shashiranjanmca05 at gmail.com>
20 *
21 * Derived from Beagle Board and 3430 SDP code by
22 * Richard Woodruff <r-woodruff2 at ti.com>
23 * Syed Mohammed Khasim <khasim at ti.com>
Tom Rix330a90a2009-06-28 12:52:29 -050024 */
25
26#include <twl4030.h>
27
28/*
29 * Power Reset
30 */
31void twl4030_power_reset_init(void)
32{
33 u8 val = 0;
Nishanth Menon5d9d6f72013-03-26 05:20:50 +000034 if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
35 TWL4030_PM_MASTER_P1_SW_EVENTS, &val)) {
Tom Rix330a90a2009-06-28 12:52:29 -050036 printf("Error:TWL4030: failed to read the power register\n");
37 printf("Could not initialize hardware reset\n");
38 } else {
39 val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
Nishanth Menond26a1062013-03-26 05:20:49 +000040 if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
41 TWL4030_PM_MASTER_P1_SW_EVENTS, val)) {
Tom Rix330a90a2009-06-28 12:52:29 -050042 printf("Error:TWL4030: failed to write the power register\n");
43 printf("Could not initialize hardware reset\n");
44 }
45 }
46}
47
Tom Rix0f2a8042009-06-28 12:52:30 -050048/*
Paul Kocialkowski8264e142015-07-20 15:17:07 +020049 * Power off
50 */
51void twl4030_power_off(void)
52{
53 u8 data;
54
55 /* PM master unlock (CFG and TST keys) */
56
57 data = 0xCE;
58 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
59 TWL4030_PM_MASTER_PROTECT_KEY, data);
60 data = 0xEC;
61 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
62 TWL4030_PM_MASTER_PROTECT_KEY, data);
63
64 /* VBAT start disable */
65
66 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
67 TWL4030_PM_MASTER_CFG_P1_TRANSITION, &data);
68 data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
69 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
70 TWL4030_PM_MASTER_CFG_P1_TRANSITION, data);
71
72 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
73 TWL4030_PM_MASTER_CFG_P2_TRANSITION, &data);
74 data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
75 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
76 TWL4030_PM_MASTER_CFG_P2_TRANSITION, data);
77
78 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
79 TWL4030_PM_MASTER_CFG_P3_TRANSITION, &data);
80 data &= ~TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT;
81 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
82 TWL4030_PM_MASTER_CFG_P3_TRANSITION, data);
83
84 /* High jitter for PWRANA2 */
85
86 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
87 TWL4030_PM_MASTER_CFG_PWRANA2, &data);
88 data &= ~(TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV |
89 TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV);
90 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
91 TWL4030_PM_MASTER_CFG_PWRANA2, data);
92
93 /* PM master lock */
94
95 data = 0xFF;
96 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
97 TWL4030_PM_MASTER_PROTECT_KEY, data);
98
99 /* Power off */
100
101 twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER,
102 TWL4030_PM_MASTER_P1_SW_EVENTS, &data);
103 data |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF;
104 twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
105 TWL4030_PM_MASTER_P1_SW_EVENTS, data);
106}
107
108/*
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700109 * Set Device Group and Voltage
Tom Rix0f2a8042009-06-28 12:52:30 -0500110 */
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700111void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
112 u8 dev_grp, u8 dev_grp_sel)
113{
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +0000114 int ret;
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700115
116 /* Select the Voltage */
Nishanth Menond26a1062013-03-26 05:20:49 +0000117 ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_reg,
118 vsel_val);
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +0000119 if (ret != 0) {
Peter Meerwaldcc2884a2012-11-19 23:13:04 +0000120 printf("Could not write vsel to reg %02x (%d)\n",
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +0000121 vsel_reg, ret);
122 return;
123 }
124
125 /* Select the Device Group (enable the supply if dev_grp_sel != 0) */
Nishanth Menond26a1062013-03-26 05:20:49 +0000126 ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp,
127 dev_grp_sel);
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +0000128 if (ret != 0)
Peter Meerwaldcc2884a2012-11-19 23:13:04 +0000129 printf("Could not write grp_sel to reg %02x (%d)\n",
Grazvydas Ignotas0fcedce2012-03-19 03:37:40 +0000130 dev_grp, ret);
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700131}
Tom Rix0f2a8042009-06-28 12:52:30 -0500132
133void twl4030_power_init(void)
134{
Tom Rix0f2a8042009-06-28 12:52:30 -0500135 /* set VAUX3 to 2.8V */
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700136 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
137 TWL4030_PM_RECEIVER_VAUX3_VSEL_28,
138 TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
139 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix0f2a8042009-06-28 12:52:30 -0500140
141 /* set VPLL2 to 1.8V */
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700142 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED,
143 TWL4030_PM_RECEIVER_VPLL2_VSEL_18,
144 TWL4030_PM_RECEIVER_VPLL2_DEV_GRP,
145 TWL4030_PM_RECEIVER_DEV_GRP_ALL);
Tom Rix0f2a8042009-06-28 12:52:30 -0500146
147 /* set VDAC to 1.8V */
Steve Sakomana18fc3f2010-08-10 12:58:39 -0700148 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
149 TWL4030_PM_RECEIVER_VDAC_VSEL_18,
150 TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
151 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix0f2a8042009-06-28 12:52:30 -0500152}
Tom Rix330a90a2009-06-28 12:52:29 -0500153
Paul Kocialkowskif745ba42014-11-08 20:55:46 +0100154void twl4030_power_mmc_init(int dev_index)
Tom Rix247e3c22009-06-28 12:52:31 -0500155{
Paul Kocialkowskif745ba42014-11-08 20:55:46 +0100156 if (dev_index == 0) {
157 /* Set VMMC1 to 3.15 Volts */
158 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
159 TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
160 TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
161 TWL4030_PM_RECEIVER_DEV_GRP_P1);
162
163 mdelay(100); /* ramp-up delay from Linux code */
164 } else if (dev_index == 1) {
165 /* Set VMMC2 to 3.15 Volts */
166 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
167 TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
168 TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
169 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Paul Kocialkowski5859f8d2014-10-28 18:14:23 +0100170
Paul Kocialkowskif745ba42014-11-08 20:55:46 +0100171 mdelay(100); /* ramp-up delay from Linux code */
172 }
Tom Rix247e3c22009-06-28 12:52:31 -0500173}