blob: 62096c24fb7bafcbbac05270c7f415bf61fd0b04 [file] [log] [blame]
Peng Fanc47e09d2019-12-30 17:46:21 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06007#include <env.h>
Peng Fanc47e09d2019-12-30 17:46:21 +08008#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Peng Fan4f0c97b2020-12-25 16:16:34 +080010#include <miiphy.h>
11#include <netdev.h>
12#include <linux/delay.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080014#include <asm/mach-imx/iomux-v3.h>
15#include <asm-generic/gpio.h>
16#include <asm/arch/imx8mp_pins.h>
Peng Fan4f0c97b2020-12-25 16:16:34 +080017#include <asm/arch/clock.h>
Peng Fanc47e09d2019-12-30 17:46:21 +080018#include <asm/arch/sys_proto.h>
19#include <asm/mach-imx/gpio.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
24#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
25
26static iomux_v3_cfg_t const uart_pads[] = {
27 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
28 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
29};
30
31static iomux_v3_cfg_t const wdog_pads[] = {
32 MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
33};
34
35int board_early_init_f(void)
36{
37 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
38
39 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
40
41 set_wdog_reset(wdog);
42
43 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
44
45 return 0;
46}
47
Peng Fan4f0c97b2020-12-25 16:16:34 +080048static void setup_fec(void)
49{
50 struct iomuxc_gpr_base_regs *gpr =
51 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
52
53 /* Enable RGMII TX clk output */
54 setbits_le32(&gpr->gpr[1], BIT(22));
55}
56
Peng Fan4f0c97b2020-12-25 16:16:34 +080057static int setup_eqos(void)
58{
59 struct iomuxc_gpr_base_regs *gpr =
60 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
61
Peng Fan4f0c97b2020-12-25 16:16:34 +080062 /* set INTF as RGMII, enable RGMII TXC clock */
63 clrsetbits_le32(&gpr->gpr[1],
64 IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
65 setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
66
67 return set_clk_eqos(ENET_125MHZ);
68}
69
70#if CONFIG_IS_ENABLED(NET)
71int board_phy_config(struct phy_device *phydev)
Peng Fanc47e09d2019-12-30 17:46:21 +080072{
Peng Fan4f0c97b2020-12-25 16:16:34 +080073 if (phydev->drv->config)
74 phydev->drv->config(phydev);
Peng Fanc47e09d2019-12-30 17:46:21 +080075 return 0;
76}
Peng Fan4f0c97b2020-12-25 16:16:34 +080077#endif
78
79int board_init(void)
80{
81 int ret = 0;
82
83 if (CONFIG_IS_ENABLED(FEC_MXC)) {
84 setup_fec();
Ye Li82da0f52021-08-16 18:44:29 +080085 }
Peng Fan4f0c97b2020-12-25 16:16:34 +080086
Ye Li82da0f52021-08-16 18:44:29 +080087 if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
88 ret = setup_eqos();
Peng Fan4f0c97b2020-12-25 16:16:34 +080089 }
90
91 return ret;
92}
Peng Fanc47e09d2019-12-30 17:46:21 +080093
94int board_late_init(void)
95{
96#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
97 env_set("board_name", "EVK");
98 env_set("board_rev", "iMX8MP");
99#endif
100
101 return 0;
102}