blob: 7ec149d178c594a9837799336480d62b2bf2c264 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shadi Ammouri3b386452016-10-27 13:29:41 +02002/*
3 * Copyright (C) 2015 Marvell International Ltd.
4 *
5 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
6 *
7 * Based on:
8 * - drivers/pci/pcie_imx.c
9 * - drivers/pci/pci_mvebu.c
10 * - drivers/pci/pcie_xilinx.c
Shadi Ammouri3b386452016-10-27 13:29:41 +020011 */
12
13#include <common.h>
14#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060015#include <log.h>
Shadi Ammouri3b386452016-10-27 13:29:41 +020016#include <pci.h>
17#include <asm/io.h>
Konstantin Porotchkin4eb09cd2017-02-08 17:34:13 +020018#include <asm-generic/gpio.h>
Simon Glassdbd79542020-05-10 11:40:11 -060019#include <linux/delay.h>
Shadi Ammouri3b386452016-10-27 13:29:41 +020020
21DECLARE_GLOBAL_DATA_PTR;
22
23/* PCI Config space registers */
24#define PCIE_CONFIG_BAR0 0x10
25#define PCIE_LINK_STATUS_REG 0x80
26#define PCIE_LINK_STATUS_SPEED_OFF 16
27#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
28#define PCIE_LINK_STATUS_WIDTH_OFF 20
29#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
30
31/* Resizable bar capability registers */
32#define RESIZABLE_BAR_CAP 0x250
33#define RESIZABLE_BAR_CTL0 0x254
34#define RESIZABLE_BAR_CTL1 0x258
35
36/* iATU registers */
37#define PCIE_ATU_VIEWPORT 0x900
38#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
39#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
40#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
41#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
42#define PCIE_ATU_CR1 0x904
43#define PCIE_ATU_TYPE_MEM (0x0 << 0)
44#define PCIE_ATU_TYPE_IO (0x2 << 0)
45#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
46#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
47#define PCIE_ATU_CR2 0x908
48#define PCIE_ATU_ENABLE (0x1 << 31)
49#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
50#define PCIE_ATU_LOWER_BASE 0x90C
51#define PCIE_ATU_UPPER_BASE 0x910
52#define PCIE_ATU_LIMIT 0x914
53#define PCIE_ATU_LOWER_TARGET 0x918
54#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
55#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
56#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
57#define PCIE_ATU_UPPER_TARGET 0x91C
58
59#define PCIE_LINK_CAPABILITY 0x7C
60#define PCIE_LINK_CTL_2 0xA0
61#define TARGET_LINK_SPEED_MASK 0xF
62#define LINK_SPEED_GEN_1 0x1
63#define LINK_SPEED_GEN_2 0x2
64#define LINK_SPEED_GEN_3 0x3
65
66#define PCIE_GEN3_RELATED 0x890
67#define GEN3_EQU_DISABLE (1 << 16)
68#define GEN3_ZRXDC_NON_COMP (1 << 0)
69
70#define PCIE_GEN3_EQU_CTRL 0x8A8
71#define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
72
73#define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
74
75#define PCIE_LINK_UP_TIMEOUT_MS 100
76
77#define PCIE_GLOBAL_CONTROL 0x8000
78#define PCIE_APP_LTSSM_EN (1 << 2)
79#define PCIE_DEVICE_TYPE_OFFSET (4)
80#define PCIE_DEVICE_TYPE_MASK (0xF)
81#define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
82#define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
83#define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
84
85#define PCIE_GLOBAL_STATUS 0x8008
86#define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
87#define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
88
89#define PCIE_ARCACHE_TRC 0x8050
90#define PCIE_AWCACHE_TRC 0x8054
91#define ARCACHE_SHAREABLE_CACHEABLE 0x3511
92#define AWCACHE_SHAREABLE_CACHEABLE 0x5311
93
94#define LINK_SPEED_GEN_1 0x1
95#define LINK_SPEED_GEN_2 0x2
96#define LINK_SPEED_GEN_3 0x3
97
98/**
99 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
100 *
101 * @ctrl_base: The base address of the register space
102 * @cfg_base: The base address of the configuration space
103 * @cfg_size: The size of the configuration space which is needed
104 * as it gets written into the PCIE_ATU_LIMIT register
105 * @first_busno: This driver supports multiple PCIe controllers.
106 * first_busno stores the bus number of the PCIe root-port
107 * number which may vary depending on the PCIe setup
108 * (PEX switches etc).
109 */
110struct pcie_dw_mvebu {
111 void *ctrl_base;
112 void *cfg_base;
113 fdt_size_t cfg_size;
114 int first_busno;
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200115
116 /* IO and MEM PCI regions */
117 struct pci_region io;
118 struct pci_region mem;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200119};
120
121static int pcie_dw_get_link_speed(const void *regs_base)
122{
123 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
124 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
125}
126
127static int pcie_dw_get_link_width(const void *regs_base)
128{
129 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
130 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
131}
132
133/**
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200134 * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
135 *
136 * @pcie: Pointer to the PCI controller state
137 * @index: ATU region index
138 * @type: ATU accsess type
139 * @cpu_addr: the physical address for the translation entry
140 * @pci_addr: the pcie bus address for the translation entry
141 * @size: the size of the translation entry
142 */
143static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
144 int type, u64 cpu_addr, u64 pci_addr,
145 u32 size)
146{
147 writel(PCIE_ATU_REGION_OUTBOUND | index,
148 pcie->ctrl_base + PCIE_ATU_VIEWPORT);
149 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
150 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
151 writel(lower_32_bits(cpu_addr + size - 1),
152 pcie->ctrl_base + PCIE_ATU_LIMIT);
153 writel(lower_32_bits(pci_addr),
154 pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
155 writel(upper_32_bits(pci_addr),
156 pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
157 writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
158 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
159}
160
161/**
Shadi Ammouri3b386452016-10-27 13:29:41 +0200162 * set_cfg_address() - Configure the PCIe controller config space access
163 *
164 * @pcie: Pointer to the PCI controller state
165 * @d: PCI device to access
166 * @where: Offset in the configuration space
167 *
168 * Configures the PCIe controller to access the configuration space of
169 * a specific PCIe device and returns the address to use for this
170 * access.
171 *
172 * Return: Address that can be used to access the configation space
173 * of the requested device / offset
174 */
175static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
176 pci_dev_t d, uint where)
177{
178 uintptr_t va_address;
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200179 u32 atu_type;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200180
181 /*
182 * Region #0 is used for Outbound CFG space access.
183 * Direction = Outbound
184 * Region Index = 0
185 */
Shadi Ammouri3b386452016-10-27 13:29:41 +0200186
187 if (PCI_BUS(d) == (pcie->first_busno + 1))
188 /* For local bus, change TLP Type field to 4. */
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200189 atu_type = PCIE_ATU_TYPE_CFG0;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200190 else
191 /* Otherwise, change TLP Type field to 5. */
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200192 atu_type = PCIE_ATU_TYPE_CFG1;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200193
194 if (PCI_BUS(d) == pcie->first_busno) {
195 /* Accessing root port configuration space. */
196 va_address = (uintptr_t)pcie->ctrl_base;
197 } else {
Minghuan Liana1c94382017-10-20 10:45:50 +0800198 d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200199 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
200 atu_type, (u64)pcie->cfg_base,
201 d << 8, pcie->cfg_size);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200202 va_address = (uintptr_t)pcie->cfg_base;
203 }
204
205 va_address += where & ~0x3;
206
207 return va_address;
208}
209
210/**
211 * pcie_dw_addr_valid() - Check for valid bus address
212 *
213 * @d: The PCI device to access
214 * @first_busno: Bus number of the PCIe controller root complex
215 *
216 * Return 1 (true) if the PCI device can be accessed by this controller.
217 *
218 * Return: 1 on valid, 0 on invalid
219 */
220static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
221{
222 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
223 return 0;
224 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
225 return 0;
226
227 return 1;
228}
229
230/**
231 * pcie_dw_mvebu_read_config() - Read from configuration space
232 *
233 * @bus: Pointer to the PCI bus
234 * @bdf: Identifies the PCIe device to access
235 * @offset: The offset into the device's configuration space
236 * @valuep: A pointer at which to store the read value
237 * @size: Indicates the size of access to perform
238 *
239 * Read a value of size @size from offset @offset within the configuration
240 * space of the device identified by the bus, device & function numbers in @bdf
241 * on the PCI bus @bus.
242 *
243 * Return: 0 on success
244 */
Simon Glass2a311e82020-01-27 08:49:37 -0700245static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf,
Shadi Ammouri3b386452016-10-27 13:29:41 +0200246 uint offset, ulong *valuep,
247 enum pci_size_t size)
248{
249 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
250 uintptr_t va_address;
251 ulong value;
252
253 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
254 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
255
256 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
257 debug("- out of range\n");
258 *valuep = pci_get_ff(size);
259 return 0;
260 }
261
262 va_address = set_cfg_address(pcie, bdf, offset);
263
264 value = readl(va_address);
265
266 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
267 *valuep = pci_conv_32_to_size(value, offset, size);
268
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200269 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
270 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
271 pcie->io.bus_start, pcie->io.size);
272
Shadi Ammouri3b386452016-10-27 13:29:41 +0200273 return 0;
274}
275
276/**
277 * pcie_dw_mvebu_write_config() - Write to configuration space
278 *
279 * @bus: Pointer to the PCI bus
280 * @bdf: Identifies the PCIe device to access
281 * @offset: The offset into the device's configuration space
282 * @value: The value to write
283 * @size: Indicates the size of access to perform
284 *
285 * Write the value @value of size @size from offset @offset within the
286 * configuration space of the device identified by the bus, device & function
287 * numbers in @bdf on the PCI bus @bus.
288 *
289 * Return: 0 on success
290 */
291static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
292 uint offset, ulong value,
293 enum pci_size_t size)
294{
295 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
296 uintptr_t va_address;
297 ulong old;
298
299 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
300 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
301 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
302
303 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
304 debug("- out of range\n");
305 return 0;
306 }
307
308 va_address = set_cfg_address(pcie, bdf, offset);
309
310 old = readl(va_address);
311 value = pci_conv_size_to_32(old, value, offset, size);
312 writel(value, va_address);
313
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200314 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
315 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
316 pcie->io.bus_start, pcie->io.size);
317
Shadi Ammouri3b386452016-10-27 13:29:41 +0200318 return 0;
319}
320
321/**
322 * pcie_dw_configure() - Configure link capabilities and speed
323 *
324 * @regs_base: A pointer to the PCIe controller registers
325 * @cap_speed: The capabilities and speed to configure
326 *
327 * Configure the link capabilities and speed in the PCIe root complex.
328 */
329static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
330{
331 /*
332 * TODO (shadi@marvell.com, sr@denx.de):
333 * Need to read the serdes speed from the dts and according to it
334 * configure the PCIe gen
335 */
336
337 /* Set link to GEN 3 */
338 clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
339 TARGET_LINK_SPEED_MASK, cap_speed);
340 clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
341 TARGET_LINK_SPEED_MASK, cap_speed);
342 setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
343}
344
345/**
346 * is_link_up() - Return the link state
347 *
348 * @regs_base: A pointer to the PCIe controller registers
349 *
350 * Return: 1 (true) for active line and 0 (false) for no link
351 */
352static int is_link_up(const void *regs_base)
353{
354 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
355 u32 reg;
356
357 reg = readl(regs_base + PCIE_GLOBAL_STATUS);
358 if ((reg & mask) == mask)
359 return 1;
360
361 return 0;
362}
363
364/**
365 * wait_link_up() - Wait for the link to come up
366 *
367 * @regs_base: A pointer to the PCIe controller registers
368 *
369 * Return: 1 (true) for active line and 0 (false) for no link (timeout)
370 */
371static int wait_link_up(const void *regs_base)
372{
373 unsigned long timeout;
374
375 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
376 while (!is_link_up(regs_base)) {
377 if (get_timer(0) > timeout)
378 return 0;
379 };
380
381 return 1;
382}
383
384/**
385 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
386 *
387 * @regs_base: A pointer to the PCIe controller registers
388 * @cap_speed: The capabilities and speed to configure
389 *
390 * Configure the PCIe controller root complex depending on the
391 * requested link capabilities and speed.
392 *
393 * Return: 1 (true) for active line and 0 (false) for no link
394 */
395static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
396{
397 if (!is_link_up(regs_base)) {
398 /* Disable LTSSM state machine to enable configuration */
399 clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
400 PCIE_APP_LTSSM_EN);
401 }
402
403 clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
404 PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
405 PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
406
407 /* Set the PCIe master AXI attributes */
408 writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
409 writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
410
411 /* DW pre link configurations */
412 pcie_dw_configure(regs_base, cap_speed);
413
414 if (!is_link_up(regs_base)) {
415 /* Configuration done. Start LTSSM */
416 setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
417 PCIE_APP_LTSSM_EN);
418 }
419
420 /* Check that link was established */
421 if (!wait_link_up(regs_base))
422 return 0;
423
424 /*
425 * Link can be established in Gen 1. still need to wait
426 * till MAC nagaotiation is completed
427 */
428 udelay(100);
429
430 return 1;
431}
432
433/**
Shadi Ammouri3b386452016-10-27 13:29:41 +0200434 * pcie_dw_set_host_bars() - Configure the host BARs
435 *
436 * @regs_base: A pointer to the PCIe controller registers
437 *
438 * Configure the host BARs of the PCIe controller root port so that
439 * PCI(e) devices may access the system memory.
440 */
441static void pcie_dw_set_host_bars(const void *regs_base)
442{
443 u32 size = gd->ram_size;
444 u64 max_size;
445 u32 reg;
446 u32 bar0;
447
448 /* Verify the maximal BAR size */
449 reg = readl(regs_base + RESIZABLE_BAR_CAP);
450 max_size = 1ULL << (5 + (reg + (1 << 4)));
451
452 if (size > max_size) {
453 size = max_size;
454 printf("Warning: PCIe BARs can't map all DRAM space\n");
455 }
456
457 /* Set the BAR base and size towards DDR */
458 bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
459 bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
460 writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
461
462 reg = ((size >> 20) - 1) << 12;
463 writel(size, regs_base + RESIZABLE_BAR_CTL0);
464}
465
466/**
467 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
468 *
469 * @dev: A pointer to the device being operated on
470 *
471 * Probe for an active link on the PCIe bus and configure the controller
472 * to enable this port.
473 *
474 * Return: 0 on success, else -ENODEV
475 */
476static int pcie_dw_mvebu_probe(struct udevice *dev)
477{
478 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
479 struct udevice *ctlr = pci_get_controller(dev);
480 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
Simon Glassfa4689a2019-12-06 21:41:35 -0700481#if CONFIG_IS_ENABLED(DM_GPIO)
Konstantin Porotchkin4eb09cd2017-02-08 17:34:13 +0200482 struct gpio_desc reset_gpio;
483
484 gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
485 GPIOD_IS_OUT);
486 /*
487 * Issue reset to add-in card trough the dedicated GPIO.
488 * Some boards are connecting the card reset pin to common system
489 * reset wire and others are using separate GPIO port.
490 * In the last case we have to release a reset of the addon card
491 * using this GPIO.
492 */
493 if (dm_gpio_is_valid(&reset_gpio)) {
Baruch Siach6e599c62019-02-03 15:15:39 +0200494 dm_gpio_set_value(&reset_gpio, 1); /* assert */
495 mdelay(200);
496 dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
Konstantin Porotchkin4eb09cd2017-02-08 17:34:13 +0200497 mdelay(200);
498 }
499#else
500 debug("PCIE Reset on GPIO support is missing\n");
Simon Glassfa4689a2019-12-06 21:41:35 -0700501#endif /* DM_GPIO */
Shadi Ammouri3b386452016-10-27 13:29:41 +0200502
Simon Glass75e534b2020-12-16 21:20:07 -0700503 pcie->first_busno = dev_seq(dev);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200504
505 /* Don't register host if link is down */
506 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
Simon Glass75e534b2020-12-16 21:20:07 -0700507 printf("PCIE-%d: Link down\n", dev_seq(dev));
Konstantin Porotchkind4739d32017-03-28 18:36:34 +0300508 } else {
Simon Glass75e534b2020-12-16 21:20:07 -0700509 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
Konstantin Porotchkind4739d32017-03-28 18:36:34 +0300510 pcie_dw_get_link_speed(pcie->ctrl_base),
511 pcie_dw_get_link_width(pcie->ctrl_base),
512 hose->first_busno);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200513 }
514
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200515 /* Store the IO and MEM windows settings for future use by the ATU */
516 pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
517 pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
518 pcie->io.size = hose->regions[0].size; /* IO size */
519
520 pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
521 pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
522 pcie->mem.size = hose->regions[1].size; /* MEM size */
523
524 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
525 PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
526 pcie->mem.bus_start, pcie->mem.size);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200527
528 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
529 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
530 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
531
532 pcie_dw_set_host_bars(pcie->ctrl_base);
533
534 return 0;
535}
536
537/**
Simon Glassaad29ae2020-12-03 16:55:21 -0700538 * pcie_dw_mvebu_of_to_plat() - Translate from DT to device state
Shadi Ammouri3b386452016-10-27 13:29:41 +0200539 *
540 * @dev: A pointer to the device being operated on
541 *
542 * Translate relevant data from the device tree pertaining to device @dev into
543 * state that the driver will later make use of. This state is stored in the
544 * device's private data structure.
545 *
546 * Return: 0 on success, else -EINVAL
547 */
Simon Glassaad29ae2020-12-03 16:55:21 -0700548static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
Shadi Ammouri3b386452016-10-27 13:29:41 +0200549{
550 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
551
552 /* Get the controller base address */
Simon Glassba1dea42017-05-17 17:18:05 -0600553 pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200554 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
555 return -EINVAL;
556
557 /* Get the config space base address and size */
Simon Glassba1dea42017-05-17 17:18:05 -0600558 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
Shadi Ammouri3b386452016-10-27 13:29:41 +0200559 &pcie->cfg_size);
560 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
561 return -EINVAL;
562
563 return 0;
564}
565
566static const struct dm_pci_ops pcie_dw_mvebu_ops = {
567 .read_config = pcie_dw_mvebu_read_config,
568 .write_config = pcie_dw_mvebu_write_config,
569};
570
571static const struct udevice_id pcie_dw_mvebu_ids[] = {
572 { .compatible = "marvell,armada8k-pcie" },
573 { }
574};
575
576U_BOOT_DRIVER(pcie_dw_mvebu) = {
577 .name = "pcie_dw_mvebu",
578 .id = UCLASS_PCI,
579 .of_match = pcie_dw_mvebu_ids,
580 .ops = &pcie_dw_mvebu_ops,
Simon Glassaad29ae2020-12-03 16:55:21 -0700581 .of_to_plat = pcie_dw_mvebu_of_to_plat,
Shadi Ammouri3b386452016-10-27 13:29:41 +0200582 .probe = pcie_dw_mvebu_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700583 .priv_auto = sizeof(struct pcie_dw_mvebu),
Shadi Ammouri3b386452016-10-27 13:29:41 +0200584};