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git01.mediatek.com / filogic / uboot / 83694567a61f960b7325ecee8c3a716f6cd213c6 / . / configs / zynq_zc770_xm013_defconfig
blob: ed6506d1ca5ebdeb86b446ff80779b9fcca1df80 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_ARM=y
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400[diff] [blame]2CONFIG_SPL_SYS_DCACHE_OFF=y
Masahiro Yamada8204bd12015-03-16 16:43:24 +0900[diff] [blame]3CONFIG_ARCH_ZYNQ=y
Michal Simek92543872016-12-16 11:57:17 +0100[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x4000000
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]5CONFIG_SPL_STACK_R_ADDR=0x200000
Michal Simek040050b2018-03-23 09:34:00 +0100[diff] [blame]6CONFIG_SPL=y
Michal Simek96794a72017-12-13 10:35:06 +0100[diff] [blame]7CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
Tien Fong Chee6fd0a712019-01-23 14:20:03 +0800[diff] [blame]8# CONFIG_SPL_FS_FAT is not set
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]9CONFIG_DISTRO_DEFAULTS=y
Ruchika Guptae9a788d2015-01-23 16:01:53 +0530[diff] [blame]10CONFIG_FIT=y
Ruchika Guptae9a788d2015-01-23 16:01:53 +0530[diff] [blame]11CONFIG_FIT_SIGNATURE=y
Jagan Teki4c57e4c2017-01-21 11:48:33 +0100[diff] [blame]12CONFIG_FIT_VERBOSE=y
Alex Kiernan0419a9b2018-04-20 21:25:38 +0000[diff] [blame]13CONFIG_IMAGE_FORMAT_LEGACY=y
Michal Simekc7abf8d2017-12-01 13:50:33 +0100[diff] [blame]14CONFIG_SPL_STACK_R=y
Heiko Schocher1d12ba22016-10-06 07:55:15 +0200[diff] [blame]15CONFIG_SPL_OS_BOOT=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]16CONFIG_SPL_SPI_LOAD=y
Siva Durga Prasad Paladugu59d461e2016-01-11 12:01:10 +0530[diff] [blame]17CONFIG_SYS_PROMPT="Zynq> "
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]18# CONFIG_CMD_FLASH is not set
Simon Glass80cb1892017-05-17 03:25:21 -0600[diff] [blame]19CONFIG_CMD_FPGA_LOADBP=y
20CONFIG_CMD_FPGA_LOADFS=y
21CONFIG_CMD_FPGA_LOADMK=y
22CONFIG_CMD_FPGA_LOADP=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]23CONFIG_CMD_GPIO=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]24# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]25CONFIG_CMD_TFTPPUT=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]26CONFIG_CMD_CACHE=y
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]27# CONFIG_SPL_DOS_PARTITION is not set
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]28# CONFIG_SPL_EFI_PARTITION is not set
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]29CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
Masahiro Yamada88e2e362015-07-17 20:26:06 +0900[diff] [blame]30CONFIG_NET_RANDOM_ETHADDR=y
Nathan Rossidd71c8a2016-01-08 03:00:46 +1000[diff] [blame]31CONFIG_SPL_DM_SEQ_ALIAS=y
Michal Simekd25aefd2018-01-09 14:52:29 +0100[diff] [blame]32CONFIG_BLK=y
Michal Simek216f6372017-11-03 15:53:56 +0100[diff] [blame]33CONFIG_FPGA_XILINX=y
Vipul Kumar4a4946b2018-02-16 18:02:51 +0530[diff] [blame]34CONFIG_FPGA_ZYNQPL=y
Michal Simek846d61b2018-01-09 15:27:31 +0100[diff] [blame]35CONFIG_DM_GPIO=y
Jagan Teki4c57e4c2017-01-21 11:48:33 +0100[diff] [blame]36# CONFIG_MMC is not set
Michal Simek7f369dc2016-01-14 13:01:44 +0100[diff] [blame]37CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]38CONFIG_SF_DEFAULT_SPEED=30000000
Michal Simekf26b4c72016-01-25 15:39:26 +0100[diff] [blame]39CONFIG_SPI_FLASH_ISSI=y
Michal Simek4d2b32d2017-11-02 10:46:15 +0100[diff] [blame]40CONFIG_SPI_FLASH_MACRONIX=y
41CONFIG_SPI_FLASH_SPANSION=y
42CONFIG_SPI_FLASH_STMICRO=y
43CONFIG_SPI_FLASH_WINBOND=y
Vipul Kumar603ca6d2018-01-24 10:51:30 +0530[diff] [blame]44CONFIG_PHY_MARVELL=y
45CONFIG_PHY_REALTEK=y
46CONFIG_PHY_XILINX=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]47CONFIG_MII=y
Michal Simek3d7285f2015-11-30 14:34:52 +0100[diff] [blame]48CONFIG_ZYNQ_GEM=y
Michal Simekab754532017-11-06 09:16:05 +0100[diff] [blame]49CONFIG_ZYNQ_SERIAL=y
Michal Simek4d2b32d2017-11-02 10:46:15 +0100[diff] [blame]50CONFIG_ZYNQ_QSPI=y