| Neil Armstrong | 5e6db8c | 2018-09-07 17:25:13 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2016 - AmLogic, Inc. |
| 4 | * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> |
| 5 | * Copyright 2018 - BayLibre, SAS |
| 6 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
| 7 | */ |
| 8 | #ifndef _ARCH_MESON_CLOCK_AXG_H_ |
| 9 | #define _ARCH_MESON_CLOCK_AXG_H_ |
| 10 | |
| 11 | /* |
| 12 | * Clock controller register offsets |
| 13 | * |
| 14 | * Register offsets from the data sheet are listed in comment blocks below. |
| 15 | * Those offsets must be multiplied by 4 before adding them to the base address |
| 16 | * to get the right value |
| 17 | */ |
| 18 | #define HHI_GP0_PLL_CNTL 0x40 |
| 19 | #define HHI_GP0_PLL_CNTL2 0x44 |
| 20 | #define HHI_GP0_PLL_CNTL3 0x48 |
| 21 | #define HHI_GP0_PLL_CNTL4 0x4c |
| 22 | #define HHI_GP0_PLL_CNTL5 0x50 |
| 23 | #define HHI_GP0_PLL_STS 0x54 |
| 24 | #define HHI_GP0_PLL_CNTL1 0x58 |
| 25 | #define HHI_HIFI_PLL_CNTL 0x80 |
| 26 | #define HHI_HIFI_PLL_CNTL2 0x84 |
| 27 | #define HHI_HIFI_PLL_CNTL3 0x88 |
| 28 | #define HHI_HIFI_PLL_CNTL4 0x8C |
| 29 | #define HHI_HIFI_PLL_CNTL5 0x90 |
| 30 | #define HHI_HIFI_PLL_STS 0x94 |
| 31 | #define HHI_HIFI_PLL_CNTL1 0x98 |
| 32 | |
| 33 | #define HHI_XTAL_DIVN_CNTL 0xbc |
| 34 | #define HHI_GCLK2_MPEG0 0xc0 |
| 35 | #define HHI_GCLK2_MPEG1 0xc4 |
| 36 | #define HHI_GCLK2_MPEG2 0xc8 |
| 37 | #define HHI_GCLK2_OTHER 0xd0 |
| 38 | #define HHI_GCLK2_AO 0xd4 |
| 39 | #define HHI_PCIE_PLL_CNTL 0xd8 |
| 40 | #define HHI_PCIE_PLL_CNTL1 0xdC |
| 41 | #define HHI_PCIE_PLL_CNTL2 0xe0 |
| 42 | #define HHI_PCIE_PLL_CNTL3 0xe4 |
| 43 | #define HHI_PCIE_PLL_CNTL4 0xe8 |
| 44 | #define HHI_PCIE_PLL_CNTL5 0xec |
| 45 | #define HHI_PCIE_PLL_CNTL6 0xf0 |
| 46 | #define HHI_PCIE_PLL_STS 0xf4 |
| 47 | |
| 48 | #define HHI_MEM_PD_REG0 0x100 |
| 49 | #define HHI_VPU_MEM_PD_REG0 0x104 |
| 50 | #define HHI_VIID_CLK_DIV 0x128 |
| 51 | #define HHI_VIID_CLK_CNTL 0x12c |
| 52 | |
| 53 | #define HHI_GCLK_MPEG0 0x140 |
| 54 | #define HHI_GCLK_MPEG1 0x144 |
| 55 | #define HHI_GCLK_MPEG2 0x148 |
| 56 | #define HHI_GCLK_OTHER 0x150 |
| 57 | #define HHI_GCLK_AO 0x154 |
| 58 | #define HHI_SYS_CPU_CLK_CNTL1 0x15c |
| 59 | #define HHI_SYS_CPU_RESET_CNTL 0x160 |
| 60 | #define HHI_VID_CLK_DIV 0x164 |
| 61 | #define HHI_SPICC_HCLK_CNTL 0x168 |
| 62 | |
| 63 | #define HHI_MPEG_CLK_CNTL 0x174 |
| 64 | #define HHI_VID_CLK_CNTL 0x17c |
| 65 | #define HHI_TS_CLK_CNTL 0x190 |
| 66 | #define HHI_VID_CLK_CNTL2 0x194 |
| 67 | #define HHI_SYS_CPU_CLK_CNTL0 0x19c |
| 68 | #define HHI_VID_PLL_CLK_DIV 0x1a0 |
| 69 | #define HHI_VPU_CLK_CNTL 0x1bC |
| 70 | |
| 71 | #define HHI_VAPBCLK_CNTL 0x1F4 |
| 72 | |
| 73 | #define HHI_GEN_CLK_CNTL 0x228 |
| 74 | |
| 75 | #define HHI_VDIN_MEAS_CLK_CNTL 0x250 |
| 76 | #define HHI_NAND_CLK_CNTL 0x25C |
| 77 | #define HHI_SD_EMMC_CLK_CNTL 0x264 |
| 78 | |
| 79 | #define HHI_MPLL_CNTL 0x280 |
| 80 | #define HHI_MPLL_CNTL2 0x284 |
| 81 | #define HHI_MPLL_CNTL3 0x288 |
| 82 | #define HHI_MPLL_CNTL4 0x28C |
| 83 | #define HHI_MPLL_CNTL5 0x290 |
| 84 | #define HHI_MPLL_CNTL6 0x294 |
| 85 | #define HHI_MPLL_CNTL7 0x298 |
| 86 | #define HHI_MPLL_CNTL8 0x29C |
| 87 | #define HHI_MPLL_CNTL9 0x2A0 |
| 88 | #define HHI_MPLL_CNTL10 0x2A4 |
| 89 | |
| 90 | #define HHI_MPLL3_CNTL0 0x2E0 |
| 91 | #define HHI_MPLL3_CNTL1 0x2E4 |
| 92 | #define HHI_PLL_TOP_MISC 0x2E8 |
| 93 | |
| 94 | #define HHI_SYS_PLL_CNTL1 0x2FC |
| 95 | #define HHI_SYS_PLL_CNTL 0x300 |
| 96 | #define HHI_SYS_PLL_CNTL2 0x304 |
| 97 | #define HHI_SYS_PLL_CNTL3 0x308 |
| 98 | #define HHI_SYS_PLL_CNTL4 0x30c |
| 99 | #define HHI_SYS_PLL_CNTL5 0x310 |
| 100 | #define HHI_SYS_PLL_STS 0x314 |
| 101 | #define HHI_DPLL_TOP_I 0x318 |
| 102 | #define HHI_DPLL_TOP2_I 0x31C |
| 103 | |
| 104 | #endif |