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git01.mediatek.com / filogic / uboot / 8367731d5616bdae012fd5574b247ce9e625ef58 / . / arch / m68k / cpu / mcf547x_8x / start.S
blob: b70842b2b83d8f7009f28adf6ee5a0af3c851f66 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]2/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]5 */
6
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]7#include <asm-offsets.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]8#include <config.h>
9#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]10#include <asm/cache.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]11
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]12#define _START _start
13#define _FAULT _fault
14
15#define SAVE_ALL \
16 move.w #0x2700,%sr; /* disable intrs */ \
17 subl #60,%sp; /* space for 15 regs */ \
18 moveml %d0-%d7/%a0-%a6,%sp@;
19
20#define RESTORE_ALL \
21 moveml %sp@,%d0-%d7/%a0-%a6; \
22 addl #60,%sp; /* space for 15 regs */ \
23 rte;
24
25.text
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]26
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]27/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]28 * Vector table. This is used for initial platform startup.
29 * These vectors are to catch any un-intended traps.
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]30 */
31_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]32INITSP: .long 0x00000000 /* Initial SP */
33INITPC: .long _START /* Initial PC */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]34
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]35vector02_0F:
36.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
37.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]38
39/* Reserved */
40vector10_17:
41.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
42
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]43vector18_1F:
44.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]45
46/* TRAP #0 - #15 */
47vector20_2F:
48.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
49.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
50
51/* Reserved */
52vector30_3F:
53.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
54.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
55
56vector64_127:
57.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65
66vector128_191:
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75
76vector192_255:
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]86.text
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]87
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]88.globl _start
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]89_start:
90 nop
91 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]92 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]93
94 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]95 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]96 movec %d0, %VBR
97
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]98 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]99 movec %d0, %RAMBAR0
100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]101 move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]102 movec %d0, %RAMBAR1
103
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]104 move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]105 move.c %d0, %MBAR
106
107 /* invalidate and disable cache */
108 move.l #0x01040100, %d0 /* Invalidate cache cmd */
109 movec %d0, %CACR /* Invalidate cache */
110 move.l #0, %d0
111 movec %d0, %ACR0
112 movec %d0, %ACR1
113 movec %d0, %ACR2
114 movec %d0, %ACR3
115
116 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]117 move.l #0, %d0
118 move.l #(ICACHE_STATUS), %a1 /* icache */
119 move.l #(DCACHE_STATUS), %a2 /* icache */
120 move.l %d0, (%a1)
121 move.l %d0, (%a2)
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]122
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]123 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]124 move.l #__got_start, %a5
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]125
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]126 /* setup stack initially on top of internal static ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]127 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]128
129 /*
130 * if configured, malloc_f arena will be reserved first,
131 * then (and always) gd struct space will be reserved
132 */
133 move.l %sp, -(%sp)
Angelo Dureghellob1924982019-03-13 21:46:44 +0100[diff] [blame]134 move.l #board_init_f_alloc_reserve, %a1
135 jsr (%a1)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]136
137 /* update stack and frame-pointers */
138 move.l %d0, %sp
139 move.l %sp, %fp
140
141 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]142 move.l %d0, -(%sp)
Angelo Dureghellob1924982019-03-13 21:46:44 +0100[diff] [blame]143 move.l #board_init_f_init_reserve, %a1
144 jsr (%a1)
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]145
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]146 /* run low-level CPU init code (from flash) */
147 jbsr cpu_init_f
148
149 /* run low-level board init code (from flash) */
150 clr.l %sp@-
151 jbsr board_init_f
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]152
153 /* board_init_f() does not return */
154
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]155/******************************************************************************/
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]156
157/*
Simon Glass284f71b2019-12-28 10:44:45 -0700[diff] [blame]158 * void relocate_code(addr_sp, gd, addr_moni)
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]159 *
160 * This "function" does not return, instead it continues in RAM
161 * after relocating the monitor code.
162 *
163 * r3 = dest
164 * r4 = src
165 * r5 = length in bytes
166 * r6 = cachelinesize
167 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]168.globl relocate_code
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]169relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]170 link.w %a6,#0
171 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]172
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]173 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
174 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]175
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]176 move.l #CONFIG_SYS_MONITOR_BASE, %a1
177 move.l #__init_end, %a2
178 move.l %a0, %a3
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]179
180 /* copy the code to RAM */
1811:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]182 move.l (%a1)+, (%a3)+
183 cmp.l %a1,%a2
184 bgt.s 1b
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]185
186/*
187 * We are done. Do not return, instead branch to second part of board
188 * initialization, now running from RAM.
189 */
190 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]191 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]192 jmp (%a1)
193
194in_ram:
195
196clear_bss:
197 /*
198 * Now clear BSS segment
199 */
200 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]201 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]202 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]203 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]2046:
205 clr.l (%a1)+
206 cmp.l %a1,%d1
207 bgt.s 6b
208
209 /*
210 * fix got table in RAM
211 */
212 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]213 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]214 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]215
216 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]217 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]218
2197:
220 move.l (%a1),%d1
221 sub.l #_start,%d1
222 add.l %a0,%d1
223 move.l %d1,(%a1)+
224 cmp.l %a2, %a1
225 bne 7b
226
227 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]228 move.l %a0, %a1
229 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]230
231 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]232 move.l %a0,-(%sp) /* dest_addr */
233 move.l %d0,-(%sp) /* gd */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]234 jsr (%a1)
235
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]236/******************************************************************************/
237
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]238/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]239.globl _fault
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]240_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]241 bra _fault
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]242
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]243.globl _exc_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]244_exc_handler:
245 SAVE_ALL
246 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]247 bsr exc_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]248 addql #4,%sp
249 RESTORE_ALL
250
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]251.globl _int_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]252_int_handler:
253 SAVE_ALL
254 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]255 bsr int_handler
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]256 addql #4,%sp
257 RESTORE_ALL
258
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]259/******************************************************************************/
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]260
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]261.globl version_string
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600[diff] [blame]262version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]263.ascii U_BOOT_VERSION_STRING, "\0"
264.align 4