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Matt Porter57da6662013-03-15 10:07:04 +00001/*
2 * hardware_ti814x.h
3 *
4 * TI814x hardware specific header
5 *
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Matt Porter57da6662013-03-15 10:07:04 +00009 */
10
11#ifndef __AM33XX_HARDWARE_TI814X_H
12#define __AM33XX_HARDWARE_TI814X_H
13
Matt Porter691fbe32013-03-15 10:07:06 +000014/* Module base addresses */
15
16/* UART Base Address */
17#define UART0_BASE 0x48020000
18
19/* Watchdog Timer */
20#define WDT_BASE 0x481C7000
21
22/* Control Module Base Address */
23#define CTRL_BASE 0x48140000
Matt Porterd4f24092013-03-20 05:38:11 +000024#define CTRL_DEVICE_BASE 0x48140600
Matt Porter691fbe32013-03-15 10:07:06 +000025
26/* PRCM Base Address */
27#define PRCM_BASE 0x48180000
Lokesh Vutla83269d02013-07-30 11:36:28 +053028#define CM_PER 0x44E00000
29#define CM_WKUP 0x44E00400
30
31#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
32#define PRM_RSTST (PRM_RSTCTRL + 8)
Matt Porter691fbe32013-03-15 10:07:06 +000033
34/* PLL Subsystem Base Address */
35#define PLL_SUBSYS_BASE 0x481C5000
36
Matt Porter57da6662013-03-15 10:07:04 +000037/* VTP Base address */
38#define VTP0_CTRL_ADDR 0x48140E0C
39
40/* DDR Base address */
41#define DDR_PHY_CMD_ADDR 0x47C0C400
42#define DDR_PHY_DATA_ADDR 0x47C0C4C8
43#define DDR_DATA_REGS_NR 4
44
Matt Porter691fbe32013-03-15 10:07:06 +000045/* CPSW Config space */
46#define CPSW_MDIO_BASE 0x4A100800
47
48/* RTC base address */
49#define RTC_BASE 0x480C0000
50
Lokesh Vutla83269d02013-07-30 11:36:28 +053051/* OTG */
52#define USB0_OTG_BASE 0x47401000
53#define USB1_OTG_BASE 0x47401800
54
Matt Porter57da6662013-03-15 10:07:04 +000055#endif /* __AM33XX_HARDWARE_TI814X_H */