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Priyanka Jainfd45ca02018-11-28 13:04:27 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2018-2021 NXP
Priyanka Jainfd45ca02018-11-28 13:04:27 +00004 */
5
6#ifndef __LX2_COMMON_H
7#define __LX2_COMMON_H
8
9#include <asm/arch/stream_id_lsch3.h>
10#include <asm/arch/config.h>
11#include <asm/arch/soc.h>
12
Priyanka Jainfd45ca02018-11-28 13:04:27 +000013#define CONFIG_FSL_MEMAC
14
15#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
16#define CONFIG_SYS_FLASH_BASE 0x20000000
17
Priyanka Jainfd45ca02018-11-28 13:04:27 +000018/* DDR */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000019#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
20#define CONFIG_VERY_BIG_RAM
21#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
22#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
23#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
24#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
25#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
Priyanka Jainfd45ca02018-11-28 13:04:27 +000026#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
27#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
28#define SPD_EEPROM_ADDRESS1 0x51
29#define SPD_EEPROM_ADDRESS2 0x52
30#define SPD_EEPROM_ADDRESS3 0x53
31#define SPD_EEPROM_ADDRESS4 0x54
32#define SPD_EEPROM_ADDRESS5 0x55
33#define SPD_EEPROM_ADDRESS6 0x56
34#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
35#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
36#define CONFIG_DIMM_SLOTS_PER_CTLR 2
Priyanka Jainfd45ca02018-11-28 13:04:27 +000037#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
38
39/* Miscellaneous configurable options */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000040
41/* SMP Definitinos */
Michael Wallef056e0f2020-06-01 21:53:26 +020042#define CPU_RELEASE_ADDR secondary_boot_addr
Priyanka Jainfd45ca02018-11-28 13:04:27 +000043
44/* Generic Timer Definitions */
45/*
46 * This is not an accurate number. It is used in start.S. The frequency
47 * will be udpated later when get_bus_freq(0) is available.
48 */
49
50#define COUNTER_FREQUENCY 25000000 /* 25MHz */
51
Priyanka Jainfd45ca02018-11-28 13:04:27 +000052/* Serial Port */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000053#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
54#define CONFIG_SYS_SERIAL0 0x21c0000
55#define CONFIG_SYS_SERIAL1 0x21d0000
56#define CONFIG_SYS_SERIAL2 0x21e0000
57#define CONFIG_SYS_SERIAL3 0x21f0000
58/*below might needs to be removed*/
59#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
60 (void *)CONFIG_SYS_SERIAL1, \
61 (void *)CONFIG_SYS_SERIAL2, \
62 (void *)CONFIG_SYS_SERIAL3 }
Priyanka Jainfd45ca02018-11-28 13:04:27 +000063
64/* MC firmware */
65#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
66#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
67#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
68#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
69#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
70
Priyanka Jainfd45ca02018-11-28 13:04:27 +000071/*
72 * Carve out a DDR region which will not be used by u-boot/Linux
73 *
74 * It will be used by MC and Debug Server. The MC region must be
75 * 512MB aligned, so the min size to hide is 512MB.
76 */
77#ifdef CONFIG_FSL_MC_ENET
Meenakshi Aggarwal67f195c2019-02-27 14:41:02 +053078#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
Priyanka Jainfd45ca02018-11-28 13:04:27 +000079#endif
80
81/* I2C bus multiplexer */
82#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
83#define I2C_MUX_CH_DEFAULT 0x8
84
85/* RTC */
86#define RTC
87#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
88
89/* EEPROM */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000090#define CONFIG_SYS_I2C_EEPROM_NXID
91#define CONFIG_SYS_EEPROM_BUS_NUM 0
Priyanka Jainfd45ca02018-11-28 13:04:27 +000092
93/* Qixis */
94#define CONFIG_FSL_QIXIS
95#define CONFIG_QIXIS_I2C_ACCESS
96#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
97
98/* PCI */
99#ifdef CONFIG_PCI
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000100#define CONFIG_PCI_SCAN_SHOW
101#endif
102
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000103/* SATA */
104
105#ifdef CONFIG_SCSI
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000106#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
107#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000108#endif
109
110/* USB */
Tom Rini8a091622021-07-09 10:11:55 -0400111#ifdef CONFIG_USB_HOST
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530112#ifndef CONFIG_TARGET_LX2162AQDS
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000113#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
114#endif
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530115#endif
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000116
Tom Rini8c70baa2021-12-14 13:36:40 -0500117#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000118
119#define CONFIG_HWCONFIG
120#define HWCONFIG_BUFFER_SIZE 128
121
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000122/* Monitor Command Prompt */
123#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
125 sizeof(CONFIG_SYS_PROMPT) + 16)
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000127#define CONFIG_SYS_MAXARGS 64 /* max command args */
128
129#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
130
131/* Initial environment variables */
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530132#define XSPI_MC_INIT_CMD \
133 "sf probe 0:0 && " \
134 "sf read 0x80640000 0x640000 0x80000 && " \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530135 "sf read $fdt_addr_r 0xf00000 0x100000 && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530136 "env exists secureboot && " \
137 "esbc_validate 0x80640000 && " \
138 "esbc_validate 0x80680000; " \
139 "sf read 0x80a00000 0xa00000 0x300000 && " \
140 "sf read 0x80e00000 0xe00000 0x100000; " \
141 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000142
143#define SD_MC_INIT_CMD \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000144 "mmc read 0x80a00000 0x5000 0x1200;" \
145 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530146 "mmc read $fdt_addr_r 0x7800 0x800;" \
Udit Agarwalf34581e2018-12-14 04:43:32 +0000147 "env exists secureboot && " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000148 "mmc read 0x80640000 0x3200 0x20 && " \
149 "mmc read 0x80680000 0x3400 0x20 && " \
150 "esbc_validate 0x80640000 && " \
151 "esbc_validate 0x80680000 ;" \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000152 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000153
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530154#define SD2_MC_INIT_CMD \
155 "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
156 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530157 "mmc read $fdt_addr_r 0x7800 0x800;" \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530158 "env exists secureboot && " \
159 "mmc read 0x80640000 0x3200 0x20 && " \
160 "mmc read 0x80680000 0x3400 0x20 && " \
161 "esbc_validate 0x80640000 && " \
162 "esbc_validate 0x80680000 ;" \
163 "fsl_mc start mc 0x80a00000 0x80e00000\0"
164
Priyanka Jain16744062019-01-24 05:22:18 +0000165#define EXTRA_ENV_SETTINGS \
166 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
167 "ramdisk_addr=0x800000\0" \
168 "ramdisk_size=0x2000000\0" \
169 "fdt_high=0xa0000000\0" \
170 "initrd_high=0xffffffffffffffff\0" \
171 "fdt_addr=0x64f00000\0" \
172 "kernel_start=0x1000000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000173 "kernelheader_start=0x600000\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000174 "scriptaddr=0x80000000\0" \
175 "scripthdraddr=0x80080000\0" \
176 "fdtheader_addr_r=0x80100000\0" \
177 "kernelheader_addr_r=0x80200000\0" \
178 "kernel_addr_r=0x81000000\0" \
179 "kernelheader_size=0x40000\0" \
180 "fdt_addr_r=0x90000000\0" \
181 "load_addr=0xa0000000\0" \
182 "kernel_size=0x2800000\0" \
183 "kernel_addr_sd=0x8000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000184 "kernelhdr_addr_sd=0x3000\0" \
Manish Tomarebef67f2020-11-05 14:08:56 +0530185 "kernel_size_sd=0x14000\0" \
Udit Agarwal11e1a572019-11-20 08:49:06 +0000186 "kernelhdr_size_sd=0x20\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000187 "console=ttyAMA0,38400n8\0" \
188 BOOTENV \
189 "mcmemsize=0x70000000\0" \
190 XSPI_MC_INIT_CMD \
Priyanka Jain16744062019-01-24 05:22:18 +0000191 "scan_dev_for_boot_part=" \
192 "part list ${devtype} ${devnum} devplist; " \
193 "env exists devplist || setenv devplist 1; " \
194 "for distro_bootpart in ${devplist}; do " \
195 "if fstype ${devtype} " \
196 "${devnum}:${distro_bootpart} " \
197 "bootfstype; then " \
198 "run scan_dev_for_boot; " \
199 "fi; " \
200 "done\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000201 "boot_a_script=" \
202 "load ${devtype} ${devnum}:${distro_bootpart} " \
203 "${scriptaddr} ${prefix}${script}; " \
204 "env exists secureboot && load ${devtype} " \
205 "${devnum}:${distro_bootpart} " \
206 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
207 "&& esbc_validate ${scripthdraddr};" \
208 "source ${scriptaddr}\0"
209
210#define XSPI_NOR_BOOTCOMMAND \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530211 "sf probe 0:0; " \
212 "sf read 0x806c0000 0x6c0000 0x40000; " \
213 "env exists mcinitcmd && env exists secureboot" \
214 " && esbc_validate 0x806c0000; " \
215 "sf read 0x80d00000 0xd00000 0x100000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000216 "env exists mcinitcmd && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530217 "fsl_mc lazyapply dpl 0x80d00000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000218 "run distro_bootcmd;run xspi_bootcmd; " \
219 "env exists secureboot && esbc_halt;"
220
221#define SD_BOOTCOMMAND \
222 "env exists mcinitcmd && mmcinfo; " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000223 "mmc read 0x80d00000 0x6800 0x800; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000224 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000225 " && mmc read 0x806C0000 0x3600 0x20 " \
226 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000227 "&& fsl_mc lazyapply dpl 0x80d00000;" \
Priyanka Jain16744062019-01-24 05:22:18 +0000228 "run distro_bootcmd;run sd_bootcmd;" \
229 "env exists secureboot && esbc_halt;"
230
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530231#define SD2_BOOTCOMMAND \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530232 "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530233 "mmc read 0x80d00000 0x6800 0x800; " \
234 "env exists mcinitcmd && env exists secureboot " \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530235 " && mmc read 0x806C0000 0x3600 0x20 " \
236 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530237 "&& fsl_mc lazyapply dpl 0x80d00000;" \
238 "run distro_bootcmd;run sd2_bootcmd;" \
239 "env exists secureboot && esbc_halt;"
240
Daniel Klauerd7daa552022-02-09 15:53:41 +0100241#ifdef CONFIG_CMD_USB
242#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
243#else
244#define BOOT_TARGET_DEVICES_USB(func)
245#endif
246
247#ifdef CONFIG_MMC
248#define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance)
249#else
250#define BOOT_TARGET_DEVICES_MMC(func)
251#endif
252
253#ifdef CONFIG_SCSI
254#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
255#else
256#define BOOT_TARGET_DEVICES_SCSI(func)
257#endif
258
259#ifdef CONFIG_CMD_DHCP
260#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
261#else
262#define BOOT_TARGET_DEVICES_DHCP(func)
263#endif
264
Priyanka Jain16744062019-01-24 05:22:18 +0000265#define BOOT_TARGET_DEVICES(func) \
Daniel Klauerd7daa552022-02-09 15:53:41 +0100266 BOOT_TARGET_DEVICES_USB(func) \
267 BOOT_TARGET_DEVICES_MMC(func, 0) \
268 BOOT_TARGET_DEVICES_MMC(func, 1) \
269 BOOT_TARGET_DEVICES_SCSI(func) \
270 BOOT_TARGET_DEVICES_DHCP(func)
Priyanka Jain16744062019-01-24 05:22:18 +0000271#include <config_distro_bootcmd.h>
272
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000273#endif /* __LX2_COMMON_H */