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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wang Huanf0ce7d62014-09-05 13:52:44 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Biwen Lid15aa9f2019-12-31 15:33:44 +08004 * Copyright 2019 NXP
Wang Huanf0ce7d62014-09-05 13:52:44 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Hongbo Zhang912b3812016-07-21 18:09:39 +080010#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
11
tang yuantian57296e72014-12-17 12:58:05 +080012#define CONFIG_DEEP_SLEEP
tang yuantian57296e72014-12-17 12:58:05 +080013
Wang Huanf0ce7d62014-09-05 13:52:44 +080014#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
15#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
16
Alison Wang34de5e42016-02-02 15:16:23 +080017#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Alison Wang2145a372014-12-09 17:38:02 +080018#define CONFIG_QIXIS_I2C_ACCESS
Alison Wang2145a372014-12-09 17:38:02 +080019#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +080020
Alison Wang9da51782014-12-03 15:00:47 +080021#ifdef CONFIG_SD_BOOT
Alison Wang9da51782014-12-03 15:00:47 +080022#define CONFIG_SPL_MAX_SIZE 0x1a000
23#define CONFIG_SPL_STACK 0x1001d000
24#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wang9da51782014-12-03 15:00:47 +080025
tang yuantian57296e72014-12-17 12:58:05 +080026#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
27 CONFIG_SYS_MONITOR_LEN)
Alison Wang9da51782014-12-03 15:00:47 +080028#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
29#define CONFIG_SPL_BSS_START_ADDR 0x80100000
30#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Alison Wang8af4c5a2015-10-30 22:45:38 +080031#define CONFIG_SYS_MONITOR_LEN 0xc0000
Alison Wang9da51782014-12-03 15:00:47 +080032#endif
33
Alison Wangab98bb52014-12-09 17:38:14 +080034#ifdef CONFIG_NAND_BOOT
Alison Wangab98bb52014-12-09 17:38:14 +080035#define CONFIG_SPL_MAX_SIZE 0x1a000
36#define CONFIG_SPL_STACK 0x1001d000
37#define CONFIG_SPL_PAD_TO 0x1c000
Alison Wangab98bb52014-12-09 17:38:14 +080038
39#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
Alison Wangab98bb52014-12-09 17:38:14 +080040#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
41#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
42
43#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
44#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
45#define CONFIG_SPL_BSS_START_ADDR 0x80100000
46#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
47#define CONFIG_SYS_MONITOR_LEN 0x80000
48#endif
49
Wang Huanf0ce7d62014-09-05 13:52:44 +080050#define SPD_EEPROM_ADDRESS 0x51
51#define CONFIG_SYS_SPD_BUS_NUM 0
Wang Huanf0ce7d62014-09-05 13:52:44 +080052
York Sunba3c0802014-09-11 13:32:07 -070053#ifndef CONFIG_SYS_FSL_DDR4
York Sunba3c0802014-09-11 13:32:07 -070054#define CONFIG_SYS_DDR_RAW_TIMING
55#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +080056#define CONFIG_DIMM_SLOTS_PER_CTLR 1
57#define CONFIG_CHIP_SELECTS_PER_CTRL 4
58
59#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
60#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
61
Wang Huanf0ce7d62014-09-05 13:52:44 +080062#ifdef CONFIG_DDR_ECC
Wang Huanf0ce7d62014-09-05 13:52:44 +080063#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
64#endif
65
Wang Huanf0ce7d62014-09-05 13:52:44 +080066/*
67 * IFC Definitions
68 */
Alison Wang34de5e42016-02-02 15:16:23 +080069#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Wang Huanf0ce7d62014-09-05 13:52:44 +080070#define CONFIG_SYS_FLASH_BASE 0x60000000
71#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
72
73#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
74#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
75 CSPR_PORT_SIZE_16 | \
76 CSPR_MSEL_NOR | \
77 CSPR_V)
78#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
79#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
80 + 0x8000000) | \
81 CSPR_PORT_SIZE_16 | \
82 CSPR_MSEL_NOR | \
83 CSPR_V)
84#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
85
86#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
87 CSOR_NOR_TRHZ_80)
88#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
89 FTIM0_NOR_TEADC(0x5) | \
90 FTIM0_NOR_TEAHC(0x5))
91#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
92 FTIM1_NOR_TRAD_NOR(0x1a) | \
93 FTIM1_NOR_TSEQRAD_NOR(0x13))
94#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
95 FTIM2_NOR_TCH(0x4) | \
96 FTIM2_NOR_TWPH(0xe) | \
97 FTIM2_NOR_TWP(0x1c))
98#define CONFIG_SYS_NOR_FTIM3 0
99
Wang Huanf0ce7d62014-09-05 13:52:44 +0800100#define CONFIG_SYS_FLASH_QUIET_TEST
101#define CONFIG_FLASH_SHOW_PROGRESS 45
102#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yaoda17d1a2014-10-17 15:26:34 +0800103#define CONFIG_SYS_WRITE_SWAPPED_DATA
Wang Huanf0ce7d62014-09-05 13:52:44 +0800104
105#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
106#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
107#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
108#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
109
110#define CONFIG_SYS_FLASH_EMPTY_INFO
111#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
112 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
113
114/*
115 * NAND Flash Definitions
116 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800117
118#define CONFIG_SYS_NAND_BASE 0x7e800000
119#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
120
121#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
122
123#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
124 | CSPR_PORT_SIZE_8 \
125 | CSPR_MSEL_NAND \
126 | CSPR_V)
127#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
128#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
129 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
130 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
131 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
132 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
133 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
134 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
135
Wang Huanf0ce7d62014-09-05 13:52:44 +0800136#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
137 FTIM0_NAND_TWP(0x18) | \
138 FTIM0_NAND_TWCHT(0x7) | \
139 FTIM0_NAND_TWH(0xa))
140#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
141 FTIM1_NAND_TWBE(0x39) | \
142 FTIM1_NAND_TRR(0xe) | \
143 FTIM1_NAND_TRP(0x18))
144#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
145 FTIM2_NAND_TREH(0xa) | \
146 FTIM2_NAND_TWHRE(0x1e))
147#define CONFIG_SYS_NAND_FTIM3 0x0
148
149#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
150#define CONFIG_SYS_MAX_NAND_DEVICE 1
Alison Wang2145a372014-12-09 17:38:02 +0800151#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800152
153/*
154 * QIXIS Definitions
155 */
156#define CONFIG_FSL_QIXIS
157
158#ifdef CONFIG_FSL_QIXIS
159#define QIXIS_BASE 0x7fb00000
160#define QIXIS_BASE_PHYS QIXIS_BASE
161#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
162#define QIXIS_LBMAP_SWITCH 6
163#define QIXIS_LBMAP_MASK 0x0f
164#define QIXIS_LBMAP_SHIFT 0
165#define QIXIS_LBMAP_DFLTBANK 0x00
166#define QIXIS_LBMAP_ALTBANK 0x04
Hongbo Zhang4f6e6102016-07-21 18:09:38 +0800167#define QIXIS_PWR_CTL 0x21
168#define QIXIS_PWR_CTL_POWEROFF 0x80
Wang Huanf0ce7d62014-09-05 13:52:44 +0800169#define QIXIS_RST_CTL_RESET 0x44
170#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
171#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
172#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Hongbo Zhangf253bbd2016-08-19 17:20:31 +0800173#define QIXIS_CTL_SYS 0x5
174#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
175#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
176#define QIXIS_RST_FORCE_3 0x45
177#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
178#define QIXIS_PWR_CTL2 0x21
179#define QIXIS_PWR_CTL2_PCTL 0x2
Wang Huanf0ce7d62014-09-05 13:52:44 +0800180
181#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
182#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
183 CSPR_PORT_SIZE_8 | \
184 CSPR_MSEL_GPCM | \
185 CSPR_V)
186#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
187#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
188 CSOR_NOR_NOR_MODE_AVD_NOR | \
189 CSOR_NOR_TRHZ_80)
190
191/*
192 * QIXIS Timing parameters for IFC GPCM
193 */
194#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
195 FTIM0_GPCM_TEADC(0xe) | \
196 FTIM0_GPCM_TEAHC(0xe))
197#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
198 FTIM1_GPCM_TRAD(0x1f))
199#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
200 FTIM2_GPCM_TCH(0xe) | \
201 FTIM2_GPCM_TWP(0xf0))
202#define CONFIG_SYS_FPGA_FTIM3 0x0
203#endif
204
Alison Wangab98bb52014-12-09 17:38:14 +0800205#if defined(CONFIG_NAND_BOOT)
206#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
207#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
208#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
209#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
210#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
211#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
212#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
213#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
214#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
215#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
216#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
217#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
218#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
219#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
220#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
221#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
222#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
223#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
224#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
225#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
226#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
227#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
228#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
229#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
230#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
231#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
232#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
233#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
234#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
235#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
236#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
237#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
238#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800239#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
240#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
241#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
242#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
243#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
244#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
245#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
246#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
247#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
248#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
249#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
250#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
251#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
252#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
253#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
254#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
255#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
256#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
257#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
258#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
259#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
260#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
261#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
262#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
263#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
264#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
265#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
266#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
267#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
268#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
269#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
270#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
Alison Wangab98bb52014-12-09 17:38:14 +0800271#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800272
273/*
274 * Serial Port
275 */
Alison Wange2f33ae2015-01-04 15:30:58 +0800276#ifdef CONFIG_LPUART
Alison Wange2f33ae2015-01-04 15:30:58 +0800277#define CONFIG_LPUART_32B_REG
278#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800279#define CONFIG_SYS_NS16550_SERIAL
York Sun89381742016-02-08 13:04:17 -0800280#ifndef CONFIG_DM_SERIAL
Wang Huanf0ce7d62014-09-05 13:52:44 +0800281#define CONFIG_SYS_NS16550_REG_SIZE 1
York Sun89381742016-02-08 13:04:17 -0800282#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800283#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Alison Wange2f33ae2015-01-04 15:30:58 +0800284#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800285
Wang Huanf0ce7d62014-09-05 13:52:44 +0800286/*
287 * I2C
288 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800289
Biwen Li4b451fd2021-02-05 19:02:03 +0800290/* GPIO */
Biwen Li4b451fd2021-02-05 19:02:03 +0800291
Jagdish Gediya013b99d2018-05-10 04:04:29 +0530292/* EEPROM */
Jagdish Gediya013b99d2018-05-10 04:04:29 +0530293#define CONFIG_SYS_I2C_EEPROM_NXID
294#define CONFIG_SYS_EEPROM_BUS_NUM 0
Jagdish Gediya013b99d2018-05-10 04:04:29 +0530295
Wang Huanf0ce7d62014-09-05 13:52:44 +0800296/*
297 * I2C bus multiplexer
298 */
299#define I2C_MUX_PCA_ADDR_PRI 0x77
300#define I2C_MUX_CH_DEFAULT 0x8
Xiubo Li27e2fe62014-12-16 14:50:33 +0800301#define I2C_MUX_CH_CH7301 0xC
Wang Huanf0ce7d62014-09-05 13:52:44 +0800302
303/*
304 * MMC
305 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800306
307/*
Xiubo Li27e2fe62014-12-16 14:50:33 +0800308 * Video
309 */
Sanchayan Maitye15479b2017-04-11 11:12:09 +0530310#ifdef CONFIG_VIDEO_FSL_DCU_FB
Xiubo Li27e2fe62014-12-16 14:50:33 +0800311#define CONFIG_VIDEO_BMP_LOGO
312
313#define CONFIG_FSL_DIU_CH7301
314#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
315#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
316#define CONFIG_SYS_I2C_DVI_ADDR 0x75
317#endif
318
319/*
Wang Huanf0ce7d62014-09-05 13:52:44 +0800320 * eTSEC
321 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800322
323#ifdef CONFIG_TSEC_ENET
Wang Huanf0ce7d62014-09-05 13:52:44 +0800324#define CONFIG_MII_DEFAULT_TSEC 3
325#define CONFIG_TSEC1 1
326#define CONFIG_TSEC1_NAME "eTSEC1"
327#define CONFIG_TSEC2 1
328#define CONFIG_TSEC2_NAME "eTSEC2"
329#define CONFIG_TSEC3 1
330#define CONFIG_TSEC3_NAME "eTSEC3"
331
332#define TSEC1_PHY_ADDR 1
333#define TSEC2_PHY_ADDR 2
334#define TSEC3_PHY_ADDR 3
335
336#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
337#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
338#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
339
340#define TSEC1_PHYIDX 0
341#define TSEC2_PHYIDX 0
342#define TSEC3_PHYIDX 0
343
344#define CONFIG_ETHPRIME "eTSEC1"
345
Wang Huanf0ce7d62014-09-05 13:52:44 +0800346#define CONFIG_HAS_ETH0
347#define CONFIG_HAS_ETH1
348#define CONFIG_HAS_ETH2
349
350#define CONFIG_FSL_SGMII_RISER 1
351#define SGMII_RISER_PHY_OFFSET 0x1b
352
353#ifdef CONFIG_FSL_SGMII_RISER
354#define CONFIG_SYS_TBIPA_VALUE 8
355#endif
356
357#endif
Minghuan Liana4d6b612014-10-31 13:43:44 +0800358
359/* PCIe */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400360#define CONFIG_PCIE1 /* PCIE controller 1 */
361#define CONFIG_PCIE2 /* PCIE controller 2 */
Minghuan Liana4d6b612014-10-31 13:43:44 +0800362
Minghuan Lian0c1593a2015-01-21 17:29:19 +0800363#ifdef CONFIG_PCI
Minghuan Lian0c1593a2015-01-21 17:29:19 +0800364#define CONFIG_PCI_SCAN_SHOW
Minghuan Lian0c1593a2015-01-21 17:29:19 +0800365#endif
366
Xiubo Li563e3ce2014-11-21 17:40:57 +0800367#define CONFIG_PEN_ADDR_BIG_ENDIAN
Mingkai Hu5b0df8a2015-10-26 19:47:41 +0800368#define CONFIG_LAYERSCAPE_NS_ACCESS
Xiubo Li563e3ce2014-11-21 17:40:57 +0800369#define CONFIG_SMP_PEN_ADDR 0x01ee0200
Andre Przywara70c78932017-02-16 01:20:19 +0000370#define COUNTER_FREQUENCY 12500000
Xiubo Li563e3ce2014-11-21 17:40:57 +0800371
Wang Huanf0ce7d62014-09-05 13:52:44 +0800372#define CONFIG_HWCONFIG
Zhuoyu Zhangfe4f2882015-08-17 18:55:12 +0800373#define HWCONFIG_BUFFER_SIZE 256
374
375#define CONFIG_FSL_DEVICE_DISABLE
Wang Huanf0ce7d62014-09-05 13:52:44 +0800376
Alison Wange2f33ae2015-01-04 15:30:58 +0800377#ifdef CONFIG_LPUART
378#define CONFIG_EXTRA_ENV_SETTINGS \
379 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
Alison Wangf6370242015-11-05 11:16:26 +0800380 "initrd_high=0xffffffff\0" \
Alison Wange2f33ae2015-01-04 15:30:58 +0800381 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
382#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800383#define CONFIG_EXTRA_ENV_SETTINGS \
384 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
Alison Wangf6370242015-11-05 11:16:26 +0800385 "initrd_high=0xffffffff\0" \
Wang Huanf0ce7d62014-09-05 13:52:44 +0800386 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
Alison Wange2f33ae2015-01-04 15:30:58 +0800387#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800388
389/*
390 * Miscellaneous configurable options
391 */
Alison Wang71477062020-02-03 15:25:19 +0800392#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wang Huanf0ce7d62014-09-05 13:52:44 +0800393
Xiubo Li03d40aa2014-11-21 17:40:59 +0800394#define CONFIG_LS102XA_STREAM_ID
395
Wang Huanf0ce7d62014-09-05 13:52:44 +0800396#define CONFIG_SYS_INIT_SP_OFFSET \
397 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
398#define CONFIG_SYS_INIT_SP_ADDR \
399 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
400
Alison Wang9da51782014-12-03 15:00:47 +0800401#ifdef CONFIG_SPL_BUILD
402#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
403#else
Wang Huanf0ce7d62014-09-05 13:52:44 +0800404#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang9da51782014-12-03 15:00:47 +0800405#endif
Wang Huanf0ce7d62014-09-05 13:52:44 +0800406
407/*
408 * Environment
409 */
Wang Huanf0ce7d62014-09-05 13:52:44 +0800410
Aneesh Bansal962021a2016-01-22 16:37:22 +0530411#include <asm/fsl_secure_boot.h>
Alison Wang13b0bb82016-01-15 15:29:32 +0800412#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Ruchika Gupta901ae762014-10-15 11:39:06 +0530413
Wang Huanf0ce7d62014-09-05 13:52:44 +0800414#endif