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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewade32cd2007-08-16 05:04:31 -05002/*
3 * Configuation settings for the esd TASREG board.
4 *
5 * (C) Copyright 2004
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
TsiChungLiewade32cd2007-08-16 05:04:31 -05007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M5249EVB_H
14#define _M5249EVB_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChungLiewade32cd2007-08-16 05:04:31 -050020#define CONFIG_MCFTMR
21
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020022#define CONFIG_SYS_UART_PORT (0)
TsiChungLiewade32cd2007-08-16 05:04:31 -050023
TsiChungLiewade32cd2007-08-16 05:04:31 -050024#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
25
26/*
27 * BOOTP options
28 */
29#undef CONFIG_BOOTP_BOOTFILESIZE
TsiChungLiewade32cd2007-08-16 05:04:31 -050030
TsiChungLiewade32cd2007-08-16 05:04:31 -050031/*
32 * Clock configuration: enable only one of the following options
33 */
34
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
36#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
37#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
TsiChungLiewade32cd2007-08-16 05:04:31 -050038
39/*
40 * Low Level Configuration Settings
41 * (address mappings, register initial values, etc.)
42 * You should know what you are doing if you make changes here.
43 */
44
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
46#define CONFIG_SYS_MBAR2 0x80000000
TsiChungLiewade32cd2007-08-16 05:04:31 -050047
48/*-----------------------------------------------------------------------
49 * Definitions for initial stack pointer and data area (in DPRAM)
50 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020052#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +020053#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiewade32cd2007-08-16 05:04:31 -050055
angelo@sysam.it6312a952015-03-29 22:54:16 +020056#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060057 . = DEFINED(env_offset) ? env_offset : .; \
58 env/embedded.o(.text);
angelo@sysam.it6312a952015-03-29 22:54:16 +020059
TsiChungLiewade32cd2007-08-16 05:04:31 -050060/*-----------------------------------------------------------------------
61 * Start addresses for the final memory configuration
62 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewade32cd2007-08-16 05:04:31 -050064 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_SDRAM_BASE 0x00000000
66#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew7f1a0462008-10-21 10:03:07 +000067#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
TsiChungLiewade32cd2007-08-16 05:04:31 -050068
69#if 0 /* test-only */
70#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
71#endif
72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChungLiewade32cd2007-08-16 05:04:31 -050074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_MONITOR_LEN 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
TsiChungLiewade32cd2007-08-16 05:04:31 -050077
78/*
79 * For booting Linux, the board info and command line data
80 * have to be in the first 8 MB of memory, since this is
81 * the maximum mapped by the Linux kernel during initialization ??
82 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiewade32cd2007-08-16 05:04:31 -050084
85/*-----------------------------------------------------------------------
86 * FLASH organization
87 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiewade32cd2007-08-16 05:04:31 -050089
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
91# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
92# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
93# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094# define CONFIG_SYS_FLASH_CHECKSUM
95# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
TsiChungLiewade32cd2007-08-16 05:04:31 -050096#endif
97
98/*-----------------------------------------------------------------------
99 * Cache Configuration
100 */
TsiChungLiewade32cd2007-08-16 05:04:31 -0500101
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600102#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200103 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600104#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200105 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600106#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
107#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
108 CF_ADDRMASK(2) | \
109 CF_ACR_EN | CF_ACR_SM_ALL)
110#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
111 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
112 CF_ACR_EN | CF_ACR_SM_ALL)
113#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
114 CF_CACR_DBWE)
115
TsiChungLiewade32cd2007-08-16 05:04:31 -0500116/*-----------------------------------------------------------------------
117 * Memory bank definitions
118 */
119
120/* CS0 - AMD Flash, address 0xffc00000 */
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000121#define CONFIG_SYS_CS0_BASE 0xffe00000
122#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
TsiChungLiewade32cd2007-08-16 05:04:31 -0500123/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000124#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
TsiChungLiewade32cd2007-08-16 05:04:31 -0500125
126/* CS1 - FPGA, address 0xe0000000 */
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000127#define CONFIG_SYS_CS1_BASE 0xe0000000
128#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
129#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
TsiChungLiewade32cd2007-08-16 05:04:31 -0500130
131/*-----------------------------------------------------------------------
132 * Port configuration
133 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
135#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
136#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
137#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
138#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
139#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
140#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChungLiewade32cd2007-08-16 05:04:31 -0500141
142#endif /* M5249 */