| Yu Chien Peter Lin | 82f0f53 | 2023-02-06 16:10:47 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2023 Andes Technology Corporation |
| 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_ANDES_CSR_H |
| 7 | #define _ASM_ANDES_CSR_H |
| 8 | |
| 9 | #include <asm/asm.h> |
| 10 | #include <linux/const.h> |
| 11 | |
| 12 | #define CSR_MCACHE_CTL 0x7ca |
| 13 | #define CSR_MMISC_CTL 0x7d0 |
| 14 | #define CSR_MARCHID 0xf12 |
| 15 | #define CSR_MCCTLCOMMAND 0x7cc |
| 16 | |
| 17 | #define MCACHE_CTL_IC_EN_OFFSET 0 |
| 18 | #define MCACHE_CTL_DC_EN_OFFSET 1 |
| 19 | #define MCACHE_CTL_CCTL_SUEN_OFFSET 8 |
| 20 | #define MCACHE_CTL_DC_COHEN_OFFSET 19 |
| 21 | #define MCACHE_CTL_DC_COHSTA_OFFSET 20 |
| 22 | |
| 23 | #define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) |
| 24 | #define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) |
| 25 | #define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) |
| 26 | #define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) |
| 27 | #define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) |
| 28 | |
| 29 | #define CCTL_L1D_WBINVAL_ALL 6 |
| 30 | |
| 31 | #endif /* _ASM_ANDES_CSR_H */ |