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git01.mediatek.com / filogic / uboot / 82c2c6aabe6fad2cc4b6960636cbabaf1f2a8c7d / . / include / asm-m68k / immap_5275.h
blob: 774866e34fac270bd878d6b2f03ab7f2e5ee61ea [file] [log] [blame]
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]1/*
2 * MCF5274/5 Internal Memory Map
3 *
4 * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
5 * Based on work Copyright (c) 2003 Josef Baumgartner
6 * <josef.baumgartner@telex.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __IMMAP_5275__
28#define __IMMAP_5275__
29
30#define MMAP_SCM (CFG_MBAR + 0x00000000)
31#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
32#define MMAP_FBCS (CFG_MBAR + 0x00000080)
33#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
34#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
35#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
36#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
37#define MMAP_UART0 (CFG_MBAR + 0x00000200)
38#define MMAP_UART1 (CFG_MBAR + 0x00000240)
39#define MMAP_UART2 (CFG_MBAR + 0x00000280)
40#define MMAP_I2C (CFG_MBAR + 0x00000300)
41#define MMAP_QSPI (CFG_MBAR + 0x00000340)
42#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
43#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
44#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
45#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
46#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
47#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
48#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
49#define MMAP_FEC0 (CFG_MBAR + 0x00001000)
50#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400)
51#define MMAP_FEC1 (CFG_MBAR + 0x00001800)
52#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00)
53#define MMAP_GPIO (CFG_MBAR + 0x00100000)
54#define MMAP_RCM (CFG_MBAR + 0x00110000)
55#define MMAP_CCM (CFG_MBAR + 0x00110004)
56#define MMAP_PLL (CFG_MBAR + 0x00120000)
57#define MMAP_EPORT (CFG_MBAR + 0x00130000)
58#define MMAP_WDOG (CFG_MBAR + 0x00140000)
59#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
60#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
61#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
62#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
63#define MMAP_MDHA (CFG_MBAR + 0x00190000)
64#define MMAP_RNG (CFG_MBAR + 0x001A0000)
65#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
66#define MMAP_USB (CFG_MBAR + 0x001C0000)
67#define MMAP_PWM0 (CFG_MBAR + 0x001D0000)
68
69/* System configuration registers
70*/
71typedef struct sys_ctrl {
72 u32 ipsbar;
73 u32 res1;
74 u32 rambar;
75 u32 res2;
76 u8 crsr;
77 u8 cwcr;
78 u8 lpicr;
79 u8 cwsr;
80 u8 res3[8];
81 u32 mpark;
82 u8 mpr;
83 u8 res4[3];
84 u8 pacr0;
85 u8 pacr1;
86 u8 pacr2;
87 u8 pacr3;
88 u8 pacr4;
89 u8 res5;
90 u8 pacr5;
91 u8 pacr6;
92 u8 pacr7;
93 u8 res6;
94 u8 pacr8;
95 u8 res7;
96 u8 gpacr;
97 u8 res8[3];
98} sysctrl_t;
99/* SDRAM controller registers, offset: 0x040
100 */
101typedef struct sdram_ctrl {
102 u32 sdmr;
103 u32 sdcr;
104 u32 sdcfg1;
105 u32 sdcfg2;
106 u32 sdbar0;
107 u32 sdbmr0;
108 u32 sdbar1;
109 u32 sdbmr1;
110} sdramctrl_t;
111
112/* Chip select module registers, offset: 0x080
113*/
114typedef struct cs_ctlr {
115 u16 ar0;
116 u16 res1;
117 u32 mr0;
118 u16 res2;
119 u16 cr0;
120 u16 ar1;
121 u16 res3;
122 u32 mr1;
123 u16 res4;
124 u16 cr1;
125 u16 ar2;
126 u16 res5;
127 u32 mr2;
128 u16 res6;
129 u16 cr2;
130 u16 ar3;
131 u16 res7;
132 u32 mr3;
133 u16 res8;
134 u16 cr3;
135 u16 ar4;
136 u16 res9;
137 u32 mr4;
138 u16 res10;
139 u16 cr4;
140 u16 ar5;
141 u16 res11;
142 u32 mr5;
143 u16 res12;
144 u16 cr5;
145 u16 ar6;
146 u16 res13;
147 u32 mr6;
148 u16 res14;
149 u16 cr6;
150 u16 ar7;
151 u16 res15;
152 u32 mr7;
153 u16 res16;
154 u16 cr7;
155} csctrl_t;
156
157/* DMA module registers, offset 0x100
158 */
159typedef struct dma_ctrl {
160 u32 sar;
161 u32 dar;
162 u32 dsrbcr;
163 u32 dcr;
164} dma_t;
165
166/* QSPI module registers, offset 0x340
167 */
168typedef struct qspi_ctrl {
169 u16 qmr;
170 u8 res1[2];
171 u16 qdlyr;
172 u8 res2[2];
173 u16 qwr;
174 u8 res3[2];
175 u16 qir;
176 u8 res4[2];
177 u16 qar;
178 u8 res5[2];
179 u16 qdr;
180 u8 res6[2];
181} qspi_t;
182
183/* Interrupt module registers, offset 0xc00
184*/
185typedef struct int_ctrl {
186 u32 iprh0;
187 u32 iprl0;
188 u32 imrh0;
189 u32 imrl0;
190 u32 frch0;
191 u32 frcl0;
192 u8 irlr;
193 u8 iacklpr;
194 u8 res1[0x26];
195 u8 icr0[64]; /* No ICR0, done this way for readability */
196 u8 res2[0x60];
197 u8 swiack0;
198 u8 res3[3];
199 u8 Lniack0_1;
200 u8 res4[3];
201 u8 Lniack0_2;
202 u8 res5[3];
203 u8 Lniack0_3;
204 u8 res6[3];
205 u8 Lniack0_4;
206 u8 res7[3];
207 u8 Lniack0_5;
208 u8 res8[3];
209 u8 Lniack0_6;
210 u8 res9[3];
211 u8 Lniack0_7;
212 u8 res10[3];
213} int0_t;
214
215/* GPIO port registers
216*/
217typedef struct gpio_ctrl {
218 /* Port Output Data Registers */
219 u8 podr_res1[4];
220 u8 podr_busctl;
221 u8 podr_addr;
222 u8 podr_res2[2];
223 u8 podr_cs;
224 u8 podr_res3;
225 u8 podr_fec0h;
226 u8 podr_fec0l;
227 u8 podr_feci2c;
228 u8 podr_qspi;
229 u8 podr_sdram;
230 u8 podr_timerh;
231 u8 podr_timerl;
232 u8 podr_uartl;
233 u8 podr_fec1h;
234 u8 podr_fec1l;
235 u8 podr_bs;
236 u8 podr_res4;
237 u8 podr_usbh;
238 u8 podr_usbl;
239 u8 podr_uarth;
240 u8 podr_res5[3];
241 /* Port Data Direction Registers */
242 u8 pddr_res1[4];
243 u8 pddr_busctl;
244 u8 pddr_addr;
245 u8 pddr_res2[2];
246 u8 pddr_cs;
247 u8 pddr_res3;
248 u8 pddr_fec0h;
249 u8 pddr_fec0l;
250 u8 pddr_feci2c;
251 u8 pddr_qspi;
252 u8 pddr_sdram;
253 u8 pddr_timerh;
254 u8 pddr_timerl;
255 u8 pddr_uartl;
256 u8 pddr_fec1h;
257 u8 pddr_fec1l;
258 u8 pddr_bs;
259 u8 pddr_res4;
260 u8 pddr_usbh;
261 u8 pddr_usbl;
262 u8 pddr_uarth;
263 u8 pddr_res5[3];
264 /* Port Pin Data/Set Registers */
265 u8 ppdsdr_res1[4];
266 u8 ppdsdr_busctl;
267 u8 ppdsdr_addr;
268 u8 ppdsdr_res2[2];
269 u8 ppdsdr_cs;
270 u8 ppdsdr_res3;
271 u8 ppdsdr_fec0h;
272 u8 ppdsdr_fec0l;
273 u8 ppdsdr_feci2c;
274 u8 ppdsdr_qspi;
275 u8 ppdsdr_sdram;
276 u8 ppdsdr_timerh;
277 u8 ppdsdr_timerl;
278 u8 ppdsdr_uartl;
279 u8 ppdsdr_fec1h;
280 u8 ppdsdr_fec1l;
281 u8 ppdsdr_bs;
282 u8 ppdsdr_res4;
283 u8 ppdsdr_usbh;
284 u8 ppdsdr_usbl;
285 u8 ppdsdr_uarth;
286 u8 ppdsdr_res5[3];
287 /* Port Clear Output Data Registers */
288 u8 pclrr_res1[4];
289 u8 pclrr_busctl;
290 u8 pclrr_addr;
291 u8 pclrr_res2[2];
292 u8 pclrr_cs;
293 u8 pclrr_res3;
294 u8 pclrr_fec0h;
295 u8 pclrr_fec0l;
296 u8 pclrr_feci2c;
297 u8 pclrr_qspi;
298 u8 pclrr_sdram;
299 u8 pclrr_timerh;
300 u8 pclrr_timerl;
301 u8 pclrr_uartl;
302 u8 pclrr_fec1h;
303 u8 pclrr_fec1l;
304 u8 pclrr_bs;
305 u8 pclrr_res4;
306 u8 pclrr_usbh;
307 u8 pclrr_usbl;
308 u8 pclrr_uarth;
309 u8 pclrr_res5[3];
310 /* Pin Assignment Registers */
311 u8 par_addr;
312 u8 par_cs;
313 u16 par_busctl;
314 u8 par_res1[2];
315 u16 par_usb;
316 u8 par_fec0hl;
317 u8 par_fec1hl;
318 u16 par_timer;
319 u16 par_uart;
320 u16 par_qspi;
321 u16 par_sdram;
322 u16 par_feci2c;
323 u8 par_bs;
324 u8 par_res2[3];
325} gpio_t;
326
327
328/* PWM module registers
329 */
330typedef struct pwm_ctrl {
331 u8 pwcr0;
332 u8 res1[3];
333 u8 pwcr1;
334 u8 res2[3];
335 u8 pwcr2;
336 u8 res3[7];
337 u8 pwwd0;
338 u8 res4[3];
339 u8 pwwd1;
340 u8 res5[3];
341 u8 pwwd2;
342 u8 res6[7];
343} pwm_t;
344
345/* Watchdog registers
346 */
347typedef struct wdog_ctrl {
348 u16 wcr;
349 u16 wmr;
350 u16 wcntr;
351 u16 wsr;
352 u8 res4[114];
353} wdog_t;
354
355/* USB module registers
356*/
357typedef struct usb {
358 u16 res1;
359 u16 fnr;
360 u16 res2;
361 u16 fnmr;
362 u16 res3;
363 u16 rfmr;
364 u16 res4;
365 u16 rfmmr;
366 u8 res5[3];
367 u8 far;
368 u32 asr;
369 u32 drr1;
370 u32 drr2;
371 u16 res6;
372 u16 specr;
373 u16 res7;
374 u16 ep0sr;
375 u32 iep0cfg;
376 u32 oep0cfg;
377 u32 ep1cfg;
378 u32 ep2cfg;
379 u32 ep3cfg;
380 u32 ep4cfg;
381 u32 ep5cfg;
382 u32 ep6cfg;
383 u32 ep7cfg;
384 u32 ep0ctl;
385 u16 res8;
386 u16 ep1ctl;
387 u16 res9;
388 u16 ep2ctl;
389 u16 res10;
390 u16 ep3ctl;
391 u16 res11;
392 u16 ep4ctl;
393 u16 res12;
394 u16 ep5ctl;
395 u16 res13;
396 u16 ep6ctl;
397 u16 res14;
398 u16 ep7ctl;
399 u32 ep0isr;
400 u16 res15;
401 u16 ep1isr;
402 u16 res16;
403 u16 ep2isr;
404 u16 res17;
405 u16 ep3isr;
406 u16 res18;
407 u16 ep4isr;
408 u16 res19;
409 u16 ep5isr;
410 u16 res20;
411 u16 ep6isr;
412 u16 res21;
413 u16 ep7isr;
414 u32 ep0imr;
415 u16 res22;
416 u16 ep1imr;
417 u16 res23;
418 u16 ep2imr;
419 u16 res24;
420 u16 ep3imr;
421 u16 res25;
422 u16 ep4imr;
423 u16 res26;
424 u16 ep5imr;
425 u16 res27;
426 u16 ep6imr;
427 u16 res28;
428 u16 ep7imr;
429 u32 ep0dr;
430 u32 ep1dr;
431 u32 ep2dr;
432 u32 ep3dr;
433 u32 ep4dr;
434 u32 ep5dr;
435 u32 ep6dr;
436 u32 ep7dr;
437 u16 res29;
438 u16 ep0dpr;
439 u16 res30;
440 u16 ep1dpr;
441 u16 res31;
442 u16 ep2dpr;
443 u16 res32;
444 u16 ep3dpr;
445 u16 res33;
446 u16 ep4dpr;
447 u16 res34;
448 u16 ep5dpr;
449 u16 res35;
450 u16 ep6dpr;
451 u16 res36;
452 u16 ep7dpr;
453 u8 res37[788];
454 u8 cfgram[1024];
455} usb_t;
456
457/* PLL module registers
458 */
459typedef struct pll_ctrl {
460 u32 syncr;
461 u32 synsr;
462} pll_t;
463
464typedef struct rcm {
465 u8 rcr;
466 u8 rsr;
467} rcm_t;
468
469#endif /* __IMMAP_5275__ */