Peng Fan | a181afe | 2019-09-16 03:09:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018-2019 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 8 | #include <command.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 9 | #include <cpu_func.h> |
Simon Glass | f11478f | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 10 | #include <hang.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 11 | #include <image.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 12 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 13 | #include <log.h> |
Peng Fan | a181afe | 2019-09-16 03:09:55 +0000 | [diff] [blame] | 14 | #include <spl.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/mach-imx/iomux-v3.h> |
| 17 | #include <asm/arch/clock.h> |
| 18 | #include <asm/arch/imx8mn_pins.h> |
| 19 | #include <asm/arch/sys_proto.h> |
| 20 | #include <asm/mach-imx/boot_mode.h> |
| 21 | #include <asm/arch/ddr.h> |
| 22 | |
| 23 | #include <dm/uclass.h> |
| 24 | #include <dm/device.h> |
| 25 | #include <dm/uclass-internal.h> |
| 26 | #include <dm/device-internal.h> |
| 27 | |
| 28 | DECLARE_GLOBAL_DATA_PTR; |
| 29 | |
| 30 | int spl_board_boot_device(enum boot_device boot_dev_spl) |
| 31 | { |
| 32 | return BOOT_DEVICE_BOOTROM; |
| 33 | } |
| 34 | |
| 35 | void spl_dram_init(void) |
| 36 | { |
| 37 | ddr_init(&dram_timing); |
| 38 | } |
| 39 | |
| 40 | void spl_board_init(void) |
| 41 | { |
| 42 | struct udevice *dev; |
| 43 | int ret; |
| 44 | |
| 45 | puts("Normal Boot\n"); |
| 46 | |
| 47 | ret = uclass_get_device_by_name(UCLASS_CLK, |
| 48 | "clock-controller@30380000", |
| 49 | &dev); |
| 50 | if (ret < 0) |
| 51 | printf("Failed to find clock node. Check device tree\n"); |
| 52 | } |
| 53 | |
| 54 | #ifdef CONFIG_SPL_LOAD_FIT |
| 55 | int board_fit_config_name_match(const char *name) |
| 56 | { |
| 57 | /* Just empty function now - can't decide what to choose */ |
| 58 | debug("%s: %s\n", __func__, name); |
| 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | #endif |
| 63 | |
| 64 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) |
| 65 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) |
| 66 | |
| 67 | static iomux_v3_cfg_t const uart_pads[] = { |
| 68 | IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 69 | IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 70 | }; |
| 71 | |
| 72 | static iomux_v3_cfg_t const wdog_pads[] = { |
| 73 | IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 74 | }; |
| 75 | |
| 76 | int board_early_init_f(void) |
| 77 | { |
| 78 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 79 | |
| 80 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| 81 | |
| 82 | set_wdog_reset(wdog); |
| 83 | |
| 84 | imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); |
| 85 | |
| 86 | init_uart_clk(1); |
| 87 | |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | void board_init_f(ulong dummy) |
| 92 | { |
| 93 | int ret; |
| 94 | |
| 95 | arch_cpu_init(); |
| 96 | |
| 97 | init_uart_clk(1); |
| 98 | |
| 99 | board_early_init_f(); |
| 100 | |
| 101 | timer_init(); |
| 102 | |
| 103 | preloader_console_init(); |
| 104 | |
| 105 | /* Clear the BSS. */ |
| 106 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 107 | |
| 108 | ret = spl_init(); |
| 109 | if (ret) { |
| 110 | debug("spl_init() failed: %d\n", ret); |
| 111 | hang(); |
| 112 | } |
| 113 | |
| 114 | enable_tzc380(); |
| 115 | |
| 116 | /* DDR initialization */ |
| 117 | spl_dram_init(); |
| 118 | |
| 119 | board_init_r(NULL, 0); |
| 120 | } |