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git01.mediatek.com / filogic / uboot / 82b5a86aa444cb4416ed45b4c4c39ed189e91b9b / . / drivers / ram / starfive / starfive_ddr.c
blob: b31ed3bcf617326436e88440238c805ae0669b73 [file] [log] [blame]
Yanhong Wangd60e8802023-03-29 11:42:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
6
Yanhong Wangd60e8802023-03-29 11:42:16 +0800[diff] [blame]7#include <asm/arch/regs.h>
8#include <asm/io.h>
9#include <clk.h>
10#include <dm.h>
11#include <fdtdec.h>
12#include <init.h>
13#include <linux/bitops.h>
14#include <linux/sizes.h>
15#include <linux/delay.h>
16#include <ram.h>
17#include <reset.h>
18
19#include "starfive_ddr.h"
20
21DECLARE_GLOBAL_DATA_PTR;
22
23struct starfive_ddr_priv {
24 struct udevice *dev;
25 struct ram_info info;
26 void __iomem *ctrlreg;
27 void __iomem *phyreg;
28 struct reset_ctl_bulk rst;
29 struct clk clk;
30 u32 fre;
31};
32
33static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
34{
35 enum ddr_size_t size;
36
37 switch (priv->info.size) {
38 case SZ_2G:
39 size = DDR_SIZE_2G;
40 break;
41
42 case SZ_4G:
43 size = DDR_SIZE_4G;
44 break;
45
46 case 0x200000000:
47 size = DDR_SIZE_8G;
48 break;
49
50 case 0x400000000:
51 default:
52 pr_err("unsupport size %lx\n", priv->info.size);
53 return -EINVAL;
54 }
55
56 ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
57 ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
58 ddr_phy_start(priv->phyreg, size);
59
60 DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
61 ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
62 priv->phyreg, size);
63
64 return 0;
65}
66
67static int starfive_ddr_probe(struct udevice *dev)
68{
69 struct starfive_ddr_priv *priv = dev_get_priv(dev);
70 fdt_addr_t addr;
71 u64 rate;
72 int ret;
73
Yanhong Wangd60e8802023-03-29 11:42:16 +0800[diff] [blame]74 priv->info.base = gd->ram_base;
75 priv->info.size = gd->ram_size;
76
77 priv->dev = dev;
78 addr = dev_read_addr_index(dev, 0);
79 if (addr == FDT_ADDR_T_NONE)
80 return -EINVAL;
81
82 priv->ctrlreg = (void __iomem *)addr;
83 addr = dev_read_addr_index(dev, 1);
84 if (addr == FDT_ADDR_T_NONE)
85 return -EINVAL;
86
87 priv->phyreg = (void __iomem *)addr;
88 ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
89 if (ret)
90 return ret;
91
92 switch (priv->fre) {
93 case 2133:
94 rate = 1066000000;
95 break;
96
97 case 2800:
98 rate = 1400000000;
99 break;
100
101 default:
102 pr_err("Unknown DDR frequency %d\n", priv->fre);
103 return -EINVAL;
104 };
105
106 ret = reset_get_bulk(dev, &priv->rst);
107 if (ret)
108 return ret;
109
110 ret = reset_deassert_bulk(&priv->rst);
111 if (ret < 0)
112 return ret;
113
114 ret = clk_get_by_index(dev, 0, &priv->clk);
115 if (ret)
116 goto err_free_reset;
117
118 ret = clk_set_rate(&priv->clk, rate);
119 if (ret < 0)
120 goto err_free_reset;
121
122 ret = starfive_ddr_setup(dev, priv);
123 printf("DDR version: dc2e84f0.\n");
124
125 return ret;
126
127err_free_reset:
128 reset_release_bulk(&priv->rst);
129
130 return ret;
131}
132
133static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
134{
135 struct starfive_ddr_priv *priv = dev_get_priv(dev);
136
137 *info = priv->info;
138
139 return 0;
140}
141
142static struct ram_ops starfive_ddr_ops = {
143 .get_info = starfive_ddr_get_info,
144};
145
146static const struct udevice_id starfive_ddr_ids[] = {
147 { .compatible = "starfive,jh7110-dmc" },
148 { }
149};
150
151U_BOOT_DRIVER(starfive_ddr) = {
152 .name = "starfive_ddr",
153 .id = UCLASS_RAM,
154 .of_match = starfive_ddr_ids,
155 .ops = &starfive_ddr_ops,
156 .probe = starfive_ddr_probe,
157 .priv_auto = sizeof(struct starfive_ddr_priv),
158};