Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Tom Warren | 61c6d0e | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. |
Tom Warren | 61c6d0e | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* Tegra30 high-level function multiplexing */ |
| 7 | |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Tom Warren | 61c6d0e | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/funcmux.h> |
| 11 | #include <asm/arch/pinmux.h> |
| 12 | |
| 13 | int funcmux_select(enum periph_id id, int config) |
| 14 | { |
| 15 | int bad_config = config != FUNCMUX_DEFAULT; |
| 16 | |
| 17 | switch (id) { |
| 18 | case PERIPH_ID_UART1: |
| 19 | switch (config) { |
| 20 | case FUNCMUX_UART1_ULPI: |
Stephen Warren | 43eed91 | 2014-03-21 12:28:59 -0600 | [diff] [blame] | 21 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1, |
| 22 | PMUX_FUNC_UARTA); |
| 23 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2, |
| 24 | PMUX_FUNC_UARTA); |
| 25 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3, |
| 26 | PMUX_FUNC_UARTA); |
| 27 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4, |
| 28 | PMUX_FUNC_UARTA); |
| 29 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1); |
| 30 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2); |
| 31 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3); |
| 32 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4); |
Tom Warren | 61c6d0e | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 33 | break; |
| 34 | } |
| 35 | break; |
| 36 | |
| 37 | /* Add other periph IDs here as needed */ |
| 38 | |
| 39 | default: |
| 40 | debug("%s: invalid periph_id %d", __func__, id); |
| 41 | return -1; |
| 42 | } |
| 43 | |
| 44 | if (bad_config) { |
| 45 | debug("%s: invalid config %d for periph_id %d", __func__, |
| 46 | config, id); |
| 47 | return -1; |
| 48 | } |
| 49 | return 0; |
| 50 | } |