Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2008 |
| 4 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 7 | #include <config.h> |
Simon Glass | 8e16b1e | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 8 | #include <init.h> |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 9 | #include <asm/processor.h> |
| 10 | #include <asm/immap_85xx.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 11 | #include <fsl_ddr_sdram.h> |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 12 | #include <asm/processor.h> |
| 13 | #include <asm/mmu.h> |
| 14 | #include <spd_sdram.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 15 | #include <linux/delay.h> |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 16 | |
| 17 | |
| 18 | #if !defined(CONFIG_SPD_EEPROM) |
| 19 | /* |
| 20 | * Autodetect onboard DDR SDRAM on 85xx platforms |
| 21 | * |
| 22 | * NOTE: Some of the hardcoded values are hardware dependant, |
| 23 | * so this should be extended for other future boards |
| 24 | * using this routine! |
| 25 | */ |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 26 | phys_size_t fixed_sdram(void) |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 27 | { |
York Sun | a21803d | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 28 | struct ccsr_ddr __iomem *ddr = |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 29 | (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR); |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * Disable memory controller. |
| 33 | */ |
| 34 | ddr->cs0_config = 0; |
| 35 | ddr->sdram_cfg = 0; |
| 36 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 37 | ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS; |
| 38 | ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG; |
| 39 | ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0; |
| 40 | ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1; |
| 41 | ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2; |
| 42 | ddr->sdram_mode = CFG_SYS_DDR_MODE; |
| 43 | ddr->sdram_interval = CFG_SYS_DDR_INTERVAL; |
| 44 | ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2; |
| 45 | ddr->sdram_clk_cntl = CFG_SYS_DDR_CLK_CONTROL; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 46 | |
| 47 | asm ("sync;isync;msync"); |
| 48 | udelay(1000); |
| 49 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 50 | ddr->sdram_cfg = CFG_SYS_DDR_CONFIG; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 51 | asm ("sync; isync; msync"); |
| 52 | udelay(1000); |
| 53 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 54 | if (get_ram_size(0, CFG_SYS_SDRAM_SIZE<<20) == CFG_SYS_SDRAM_SIZE<<20) { |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 55 | /* |
| 56 | * OK, size detected -> all done |
| 57 | */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 58 | return CFG_SYS_SDRAM_SIZE<<20; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | return 0; /* nothing found ! */ |
| 62 | } |
| 63 | #endif |
| 64 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 65 | #if defined(CFG_SYS_DRAM_TEST) |
Simon Glass | 0ffd9db | 2019-12-28 10:45:06 -0700 | [diff] [blame] | 66 | int testdram(void) |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 67 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
| 69 | uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 70 | uint *p; |
| 71 | |
| 72 | printf ("SDRAM test phase 1:\n"); |
| 73 | for (p = pstart; p < pend; p++) |
| 74 | *p = 0xaaaaaaaa; |
| 75 | |
| 76 | for (p = pstart; p < pend; p++) { |
| 77 | if (*p != 0xaaaaaaaa) { |
| 78 | printf ("SDRAM test fails at: %08x\n", (uint) p); |
| 79 | return 1; |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | printf ("SDRAM test phase 2:\n"); |
| 84 | for (p = pstart; p < pend; p++) |
| 85 | *p = 0x55555555; |
| 86 | |
| 87 | for (p = pstart; p < pend; p++) { |
| 88 | if (*p != 0x55555555) { |
| 89 | printf ("SDRAM test fails at: %08x\n", (uint) p); |
| 90 | return 1; |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | printf ("SDRAM test passed.\n"); |
| 95 | return 0; |
| 96 | } |
| 97 | #endif |