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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkaffae2b2002-08-17 09:36:01 +00005 */
6
Simon Glass63334482019-11-14 12:57:39 -07007#include <cpu_func.h>
Stefan Roeseeff3a0a2007-10-31 17:55:58 +01008#include <asm/cache.h>
Yuri Tikhonov18db5a62008-04-29 13:32:45 +02009#include <watchdog.h>
wdenk359733b2003-03-31 17:27:09 +000010
Rasmus Villemoesdc322752021-04-21 11:16:03 +020011static ulong maybe_watchdog_reset(ulong flushed)
12{
13 flushed += CONFIG_SYS_CACHELINE_SIZE;
14 if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
Stefan Roese80877fa2022-09-02 14:10:46 +020015 schedule();
Rasmus Villemoesdc322752021-04-21 11:16:03 +020016 flushed = 0;
17 }
18 return flushed;
19}
20
Dave Liu06ed90b2008-12-05 15:36:14 +080021void flush_cache(ulong start_addr, ulong size)
wdenkaffae2b2002-08-17 09:36:01 +000022{
Dave Liu06ed90b2008-12-05 15:36:14 +080023 ulong addr, start, end;
Rasmus Villemoesdc322752021-04-21 11:16:03 +020024 ulong flushed = 0;
wdenkaffae2b2002-08-17 09:36:01 +000025
Dave Liu06ed90b2008-12-05 15:36:14 +080026 start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
27 end = start_addr + size - 1;
wdenkaffae2b2002-08-17 09:36:01 +000028
Kumar Gala3b967ae2009-02-06 08:08:06 -060029 for (addr = start; (addr <= end) && (addr >= start);
30 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080031 asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
Rasmus Villemoesdc322752021-04-21 11:16:03 +020032 flushed = maybe_watchdog_reset(flushed);
Dave Liu06ed90b2008-12-05 15:36:14 +080033 }
34 /* wait for all dcbst to complete on bus */
35 asm volatile("sync" : : : "memory");
36
Kumar Gala3b967ae2009-02-06 08:08:06 -060037 for (addr = start; (addr <= end) && (addr >= start);
38 addr += CONFIG_SYS_CACHELINE_SIZE) {
Dave Liu06ed90b2008-12-05 15:36:14 +080039 asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
Rasmus Villemoesdc322752021-04-21 11:16:03 +020040 flushed = maybe_watchdog_reset(flushed);
wdenkaffae2b2002-08-17 09:36:01 +000041 }
Dave Liu06ed90b2008-12-05 15:36:14 +080042 asm volatile("sync" : : : "memory");
43 /* flush prefetch queue */
44 asm volatile("isync" : : : "memory");
wdenkaffae2b2002-08-17 09:36:01 +000045}