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git01.mediatek.com / filogic / uboot / 82b5a86aa444cb4416ed45b4c4c39ed189e91b9b / . / arch / powerpc / cpu / mpc85xx / p4080_serdes.c
blob: 438fd446be36b43aa8157a8e0327eda9105280a4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]2/*
3 * Copyright 2009-2010 Freescale Semiconductor, Inc.
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]4 */
5
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]6#include <asm/io.h>
7#include <asm/fsl_serdes.h>
8#include <asm/processor.h>
9#include <asm/io.h>
10#include "fsl_corenet_serdes.h"
11
12static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
13 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
14 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
15 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
16 [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
17 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
18 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
19 [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
20 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
21 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
22 [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
23 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
24 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
25 [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
26 SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
27 XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
28 [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
29 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
30 XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
31 [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
32 SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
33 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
34 NONE, NONE, NONE, NONE},
35 [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
36 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
37 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
38 [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
39 AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
40 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
41 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
42 [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
43 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
44 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
45 [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
46 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
47 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
48 [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
49 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
50 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
51 [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
52 AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
53 XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
54};
55
Kumar Gala779a5322010-07-13 00:39:46 -0500[diff] [blame]56#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
57uint16_t srds_lpd_b[SRDS_MAX_BANK];
58#endif
59
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]60enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
61{
62 if (!serdes_lane_enabled(lane))
63 return NONE;
64
65 return serdes_cfg_tbl[cfg][lane];
66}
67
68int is_serdes_prtcl_valid(u32 prtcl) {
69 int i;
70
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]71 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]72 return 0;
73
74 for (i = 0; i < SRDS_MAX_LANES; i++) {
75 if (serdes_cfg_tbl[prtcl][i] != NONE)
76 return 1;
77 }
78
79 return 0;
80}